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Bram Nauta - One of the best experts on this subject based on the ideXlab platform.

  • 2 4 ghz highly selective iot receiver front end with power optimized lnta frequency divider and baseband analog fir filter
    IEEE Journal of Solid-state Circuits, 2021
    Co-Authors: Bart J Thijssen, Eric A M Klumperink, Philip Quinlan, Bram Nauta
    Abstract:

    High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2 $\times $ compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal–oxide–semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm2. It consumes 370 $\mu \text{W}$ from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has −7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a −22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel Rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.

  • 2 4 ghz highly selective iot receiver front end with power optimized lnta frequency divider and baseband analog fir filter
    IEEE Journal of Solid-state Circuits, 2020
    Co-Authors: Bart J Thijssen, Eric A M Klumperink, Philip Quinlan, Bram Nauta
    Abstract:

    High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2x compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal-oxide-semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm². It consumes 370 μW from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has -7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a -22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel Rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.

Bart J Thijssen - One of the best experts on this subject based on the ideXlab platform.

  • 2 4 ghz highly selective iot receiver front end with power optimized lnta frequency divider and baseband analog fir filter
    IEEE Journal of Solid-state Circuits, 2021
    Co-Authors: Bart J Thijssen, Eric A M Klumperink, Philip Quinlan, Bram Nauta
    Abstract:

    High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2 $\times $ compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal–oxide–semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm2. It consumes 370 $\mu \text{W}$ from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has −7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a −22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel Rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.

  • 2 4 ghz highly selective iot receiver front end with power optimized lnta frequency divider and baseband analog fir filter
    IEEE Journal of Solid-state Circuits, 2020
    Co-Authors: Bart J Thijssen, Eric A M Klumperink, Philip Quinlan, Bram Nauta
    Abstract:

    High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2x compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal-oxide-semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm². It consumes 370 μW from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has -7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a -22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel Rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.

Eric A M Klumperink - One of the best experts on this subject based on the ideXlab platform.

  • 2 4 ghz highly selective iot receiver front end with power optimized lnta frequency divider and baseband analog fir filter
    IEEE Journal of Solid-state Circuits, 2021
    Co-Authors: Bart J Thijssen, Eric A M Klumperink, Philip Quinlan, Bram Nauta
    Abstract:

    High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2 $\times $ compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal–oxide–semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm2. It consumes 370 $\mu \text{W}$ from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has −7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a −22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel Rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.

  • 2 4 ghz highly selective iot receiver front end with power optimized lnta frequency divider and baseband analog fir filter
    IEEE Journal of Solid-state Circuits, 2020
    Co-Authors: Bart J Thijssen, Eric A M Klumperink, Philip Quinlan, Bram Nauta
    Abstract:

    High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2x compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal-oxide-semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm². It consumes 370 μW from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has -7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a -22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel Rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.

Philip Quinlan - One of the best experts on this subject based on the ideXlab platform.

  • 2 4 ghz highly selective iot receiver front end with power optimized lnta frequency divider and baseband analog fir filter
    IEEE Journal of Solid-state Circuits, 2021
    Co-Authors: Bart J Thijssen, Eric A M Klumperink, Philip Quinlan, Bram Nauta
    Abstract:

    High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2 $\times $ compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal–oxide–semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm2. It consumes 370 $\mu \text{W}$ from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has −7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a −22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel Rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.

  • 2 4 ghz highly selective iot receiver front end with power optimized lnta frequency divider and baseband analog fir filter
    IEEE Journal of Solid-state Circuits, 2020
    Co-Authors: Bart J Thijssen, Eric A M Klumperink, Philip Quinlan, Bram Nauta
    Abstract:

    High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2x compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal-oxide-semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm². It consumes 370 μW from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has -7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a -22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel Rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.

D Uday - One of the best experts on this subject based on the ideXlab platform.

  • design analysis and implementation of analog complex filter for low if wireless lan application
    International Conference on VLSI Design, 2004
    Co-Authors: T H Teo, E S Khoo, D Uday, C B Tear
    Abstract:

    The design and implementation of an analog complex filter for low-IF WLAN 802.11a receiver is described. An IF of 20 MHz is chosen as a trade off between image-Rejection and power consumption. The specified bandwidth is 20 MHz. Baseband processing requires low group-delay variation in the received signal to meet bit error rate (BER) specification. This requires a design of high frequency, wide bandwidth and high attenuation filter. To resolve these issues, fifth-order complex transitional Bessel-Chebyshev filter is implemented to compromise between high attenuation and low group-delay variation. Measured results show the designed filter provides 30 dB to 40 dB image Rejection and 18 dB adjacent channel Rejection, while keeping a low group-delay variation of below 6.0 ns within the pass-band. High frequency and wide bandwidth filter also requires stringent design specification of the circuitries. Differential inverter transconductor is optimized for this continuous-time filter design. The complete filter including on-chip tuning circuit and bandgap consumes only 7.5 mA with 1.8 V single supply voltage. The circuit is fabricated using 0.18 /spl mu/m, 6-metal-single-poly CMOS process.

  • gm c complex transitional filter for low if wireless lan application
    IEEE International Conference on Fuzzy Systems, 2003
    Co-Authors: T H Teo, E S Khoo, D Uday
    Abstract:

    The design and implementation of a gm-C complex filter for low-IF WLAN is described. Fifth-order transitional complex Bessel-Chebyshev filter is implemented to compromise between high attenuation and low group-delay variation. The circuit is fabricated using 0.18 /spl mu/m CMOS process. Measured results show that the filter provides 30 dB to 40 dB image Rejection and 18 dB adjacent channel Rejection, while keeping a low group-delay variation of below 6.0ns within the pass-band. High frequency and wide bandwidth filter also requires stringent design specification of the circuitries. Differential inverter transconductor is optimized for this gm-C continuous-time filter design. The complete filter including on-chip tuning circuit and bandgap consumes only 7.5 mA with 1.8 V single supply voltage.