The Experts below are selected from a list of 98391 Experts worldwide ranked by ideXlab platform
Unku Moon - One of the best experts on this subject based on the ideXlab platform.
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an on chip calibration technique for reducing Supply Voltage sensitivity in ring oscillators
IEEE Journal of Solid-state Circuits, 2007Co-Authors: Kartikeya Mayaram, Unku MoonAbstract:A technique for reducing the Supply Voltage sensitivity of a ring oscillator using on-chip calibration is described. A 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO Supply noise over operating frequencies of 0.5 to 2 GHz. In the presence of a 10-mV 1-MHz VCO Supply noise, the measured rms jitter of the proposed PLL with on-chip calibration is 3.95 ps at a 1.4-GHz operating frequency, while a conventional design measures 8.22 ps rms jitter. For 10-MHz VCO Supply noise, the measured rms jitter is improved from 16.8 ps to 3.97 ps. The total power consumption of the PLL is 9.6 mW at 1.4 GHz, and the combined core die area of the PLL and the calibration circuitry is 0.064 mm2
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an on chip calibration technique for reducing Supply Voltage sensitivity in ring oscillators
Symposium on VLSI Circuits, 2006Co-Authors: Kartikeya Mayaram, Unku MoonAbstract:A technique for reducing ring oscillator Supply Voltage sensitivity using on-chip calibration is described. A 1V 0.13mum CMOS PLL demonstrates robust performance against VCO Supply noise over operating frequencies of 500MHz-2GHz. The measured rms jitter of the proposed PLL with on-chip calibration is 4.4ps for an operating frequency of 1.4GHz in the presence of 10mV 1MHz VCO Supply noise, while a conventional VCO measures 19.4ps rms jitter. The total power consumption of the PLL is 9.4mW, and the core die area of the PLL with calibration circuitry is 0.064mm2
S K Panda - One of the best experts on this subject based on the ideXlab platform.
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analysis of the instantaneous power flow for three phase pwm boost rectifier under unbalanced Supply Voltage conditions
IEEE Transactions on Power Electronics, 2008Co-Authors: S K PandaAbstract:This paper proposes the analysis of the instantaneous power flow of three-phase pulse-width modulation (PWM) boost rectifier under unbalanced Supply Voltage conditions. An analytical expression for the instantaneous output power has been derived, which provides the link between the output dc link Voltage and the instantaneous output power. A direct relationship between the dc link Voltage ripples and the second harmonic component in the instantaneous output power has been established. Based on the input and output instantaneous power analytical expressions provided, the presence of the odd order harmonic components in the ac line currents can be explained. A simple cascaded PI control scheme has been developed for the dc output Voltage control. The controller ensures that the dc link Voltage is maintained constant and the Supply side power factor is kept close to unity under the unbalanced Supply Voltage operating conditions. Simulation and experimental test results are provided on a 1.6-kVA laboratory-based PWM rectifier to validate the proposed analysis and control scheme.
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analysis and experimental validation of the output Voltage and input current performances in three phase pwm boost rectifiers under unbalanced and distorted Supply Voltage conditions
International Conference on Control Applications, 2007Co-Authors: S K PandaAbstract:This paper analyzes the dc output Voltage and line side currents of the three phase PWM boost rectifier under unbalanced and distorted Supply Voltage conditions. Based on the mathematical model of the three-phase PWM boost rectifier in the positive and negative synchronous rotating frames, a detailed analytical expression for the dc link Voltage has been derived and presented. It shows the presence of even order harmonic components in the dc output Voltage caused by the negative sequence component of the Supply Voltages. The effect of the distorted Supply Voltage on the line side currents has been investigated from the analytical point of view and discussed in this paper. A simple cascaded PI current control scheme in the positive and negative synchronous rotating reference frames has been designed to ensure that the dc link Voltage is maintained constant and the Supply side power factor is kept close to unity under the unbalanced and distorted Supply Voltage operating conditions. Experimental test results with the proposed controller are provided on a 1.6 kVA laboratory based PWM rectifier. Test results obtained confirm that the performance of the proposed control scheme enhances the performance of the PWM rectifier over the conventional single reference frame based controller.
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analysis and control of the output instantaneous power for three phase pwm boost rectifier under unbalanced Supply Voltage conditions
Conference of the Industrial Electronics Society, 2006Co-Authors: S K PandaAbstract:This paper proposes a new method to analyze the output instantaneous power of the three phase PWM boost rectifier under unbalanced Supply Voltage conditions. An analytical expression for the output instantaneous power has been derived and presented, which provides the link between the output dc linkage Voltage and the instantaneous output power. Based on the mathematical model of the three phase PWM rectifier in the rotating synchronous frame, the physical concept of the output instantaneous power has been explained from the analytical point of view. A direct relationship between the dc link Voltage ripples and the second harmonic component in the instantaneous output power has been derived. A simple cascaded PI control scheme has been developed for the dc output Voltage control. The controller ensures that the dc link Voltage is maintained constant and the Supply side power factor is kept close to unity under the unbalanced Supply Voltage operating conditions. Simulation and experimental test results are provided on a 1.6 kVA laboratory based PWM rectifier to validate the proposed analysis and control scheme.
Kartikeya Mayaram - One of the best experts on this subject based on the ideXlab platform.
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an on chip calibration technique for reducing Supply Voltage sensitivity in ring oscillators
IEEE Journal of Solid-state Circuits, 2007Co-Authors: Kartikeya Mayaram, Unku MoonAbstract:A technique for reducing the Supply Voltage sensitivity of a ring oscillator using on-chip calibration is described. A 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO Supply noise over operating frequencies of 0.5 to 2 GHz. In the presence of a 10-mV 1-MHz VCO Supply noise, the measured rms jitter of the proposed PLL with on-chip calibration is 3.95 ps at a 1.4-GHz operating frequency, while a conventional design measures 8.22 ps rms jitter. For 10-MHz VCO Supply noise, the measured rms jitter is improved from 16.8 ps to 3.97 ps. The total power consumption of the PLL is 9.6 mW at 1.4 GHz, and the combined core die area of the PLL and the calibration circuitry is 0.064 mm2
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an on chip calibration technique for reducing Supply Voltage sensitivity in ring oscillators
Symposium on VLSI Circuits, 2006Co-Authors: Kartikeya Mayaram, Unku MoonAbstract:A technique for reducing ring oscillator Supply Voltage sensitivity using on-chip calibration is described. A 1V 0.13mum CMOS PLL demonstrates robust performance against VCO Supply noise over operating frequencies of 500MHz-2GHz. The measured rms jitter of the proposed PLL with on-chip calibration is 4.4ps for an operating frequency of 1.4GHz in the presence of 10mV 1MHz VCO Supply noise, while a conventional VCO measures 19.4ps rms jitter. The total power consumption of the PLL is 9.4mW, and the core die area of the PLL with calibration circuitry is 0.064mm2
Jun Fan - One of the best experts on this subject based on the ideXlab platform.
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analytical probability density calculation for step pulse response of a single ended buffer with arbitrary power Supply Voltage fluctuations
IEEE Transactions on Circuits and Systems, 2014Co-Authors: Jingook Kim, Jun Ho Lee, Sunki Cho, Chulsoon Hwang, Chang Wook Yoon, Jun FanAbstract:An analytical methodology to calculate the probability density functions (PDFs) for the step pulse response of a single-ended buffer with arbitrary power-Supply Voltage fluctuations is proposed. To validate the theory, a silicon IC with noise-aggressing buffers and a victim buffer was designed, fabricated, and assembled in a printed circuit board (PCB). The overall power distribution network (PDN) of the IC and PCB was modeled from impedance measurements. The PDFs of the step pulse response of the victim buffer with power-Supply Voltage fluctuations were calculated and validated by comparisons with HSPICE and experimental results. The obtained PDFs due to power-Supply Voltage fluctuations could be combined with the statistical link simulation methods for quick estimation of bit error rate (BER).
Tadahiro Kuroda - One of the best experts on this subject based on the ideXlab platform.
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a top down low power design technique using clustered Voltage scaling with variable Supply Voltage scheme
Custom Integrated Circuits Conference, 1998Co-Authors: M Hamada, M Takahashi, Hideho Arakida, A Chiba, T Terazawa, Takashi Ishikawa, Masahiro Kanazawa, Mutsunori Igarashi, Kimiyoshi Usami, Tadahiro KurodaAbstract:A novel design technique which combines a variable Supply-Voltage scheme and a clustered Voltage scaling is presented (VS-CVS scheme). A theory to choose the optimum Supply Voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay and area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit performance compared to a conventional CMOS design.
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variable Supply Voltage scheme for low power high speed cmos digital design
IEEE Journal of Solid-state Circuits, 1998Co-Authors: Tadahiro Kuroda, A Chiba, Kojiro Suzuki, Shinji Mita, T Fujita, F Yamane, F Sano, Y WatanabeAbstract:This paper describes a variable Supply-Voltage (VS) scheme. From an external Supply, the VS scheme automatically generates minimum internal Supply Voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-/spl mu/m CMOS technology which optimally controls the internal supple Voltages with the VS scheme and the threshold Voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design.
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a 300 mips w risc core processor with variable Supply Voltage scheme in variable threshold Voltage cmos
Custom Integrated Circuits Conference, 1997Co-Authors: Kazuhiro Suzuki, A Chiba, Shinji Mita, T Fujita, F Yamane, F Sano, Y Watanabe, K Matsuda, T Maeda, Tadahiro KurodaAbstract:A 300 MIPS/W RISC core processor with variable Supply-Voltage (VS) scheme in variable threshold-Voltage CMOS (VTCMOS) is presented. Performance in MIPS/W can be improved by a factor of more than two with no modification in the RISC core except for substrate contacts for the VTCMOS. From a 3.3 V external power Supply the VS scheme automatically generates minimum internal Supply Voltages which meet the demand on its operation frequency.
