The Experts below are selected from a list of 32010 Experts worldwide ranked by ideXlab platform
Alexander Fish - One of the best experts on this subject based on the ideXlab platform.
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live demo an 88fj 40 mhz 0 4v 0 61pj 1ghz 0 9v dual mode logic 8 8 bit multiplier accumulator with a self Adjustment Mechanism in 28 nm fd soi
International Symposium on Circuits and Systems, 2019Co-Authors: Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander FishAbstract:The unique ability of dual mode logic (DML) to self-adapt to computational needs by providing high speed and/or low energy consumption is demonstrated for the first time by silicon measurements in 28nm FD-SOI. At the gate level, the DML design offers the possibility to operate either in the static mode to save energy, or in the dynamic mode to increase speed albeit with higher delay or energy consumption, respectively. In this demonstration, the two operational modes are dynamically managed by a self-Adjustment Mechanism to increase speed or reduce energy of the design at run-time. As a test case a two-stage pipelined multiply-accumulate (MAC) circuit was selected to assess the advantages of DML in terms of speed, energy and area as compared to a conventional CMOS design. We show that the self-adjusted DML MAC achieves both a performance boost of up to 92% and 16% less energy consumption than the equivalent standard CMOS implementation. The energy saved can be even greater (−35%) when the low-power (fully static) mode is enabled. In addition, the DML MAC occupies 25% less area.
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an 88 fj 40 mhz 0 4 v 0 61 pj 1 ghz 0 9 v dual mode logic 8 times 8 bit multiplier accumulator with a self Adjustment Mechanism in 28 nm fd soi
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander FishAbstract:The unique ability of dual-mode logic (DML) to self-adapt to computational needs by providing high speed and/or low energy consumption is demonstrated for the first time by silicon measurements in 28-nm fully depleted silicon on insulator. At the gate level, the DML design offers the possibility to operate either in the static mode to save energy or in the dynamic mode to increase speed, albeit with higher delay or energy consumption, respectively. In this paper, these two operational modes of the DML gates are optimally managed by a self-Adjustment Mechanism to increase speed or reduce the energy of gates/blocks in the design at run time. As a test case, a two-stage pipelined multiply–accumulate (MAC) circuit was selected to assess the advantages of DML in terms of speed, energy, and area as compared to a conventional CMOS design. We show that the self-adjusted DML MAC achieves both a performance boost of up to 92% and 16% less energy consumption than the equivalent standard CMOS implementation. The energy saved can be even greater (up to 35%) when the low-power (fully static) mode is enabled. In addition, the DML MAC occupies 25% less area.
Ramiro Taco - One of the best experts on this subject based on the ideXlab platform.
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live demo an 88fj 40 mhz 0 4v 0 61pj 1ghz 0 9v dual mode logic 8 8 bit multiplier accumulator with a self Adjustment Mechanism in 28 nm fd soi
International Symposium on Circuits and Systems, 2019Co-Authors: Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander FishAbstract:The unique ability of dual mode logic (DML) to self-adapt to computational needs by providing high speed and/or low energy consumption is demonstrated for the first time by silicon measurements in 28nm FD-SOI. At the gate level, the DML design offers the possibility to operate either in the static mode to save energy, or in the dynamic mode to increase speed albeit with higher delay or energy consumption, respectively. In this demonstration, the two operational modes are dynamically managed by a self-Adjustment Mechanism to increase speed or reduce energy of the design at run-time. As a test case a two-stage pipelined multiply-accumulate (MAC) circuit was selected to assess the advantages of DML in terms of speed, energy and area as compared to a conventional CMOS design. We show that the self-adjusted DML MAC achieves both a performance boost of up to 92% and 16% less energy consumption than the equivalent standard CMOS implementation. The energy saved can be even greater (−35%) when the low-power (fully static) mode is enabled. In addition, the DML MAC occupies 25% less area.
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an 88 fj 40 mhz 0 4 v 0 61 pj 1 ghz 0 9 v dual mode logic 8 times 8 bit multiplier accumulator with a self Adjustment Mechanism in 28 nm fd soi
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander FishAbstract:The unique ability of dual-mode logic (DML) to self-adapt to computational needs by providing high speed and/or low energy consumption is demonstrated for the first time by silicon measurements in 28-nm fully depleted silicon on insulator. At the gate level, the DML design offers the possibility to operate either in the static mode to save energy or in the dynamic mode to increase speed, albeit with higher delay or energy consumption, respectively. In this paper, these two operational modes of the DML gates are optimally managed by a self-Adjustment Mechanism to increase speed or reduce the energy of gates/blocks in the design at run time. As a test case, a two-stage pipelined multiply–accumulate (MAC) circuit was selected to assess the advantages of DML in terms of speed, energy, and area as compared to a conventional CMOS design. We show that the self-adjusted DML MAC achieves both a performance boost of up to 92% and 16% less energy consumption than the equivalent standard CMOS implementation. The energy saved can be even greater (up to 35%) when the low-power (fully static) mode is enabled. In addition, the DML MAC occupies 25% less area.
Jeanjacques E Slotine - One of the best experts on this subject based on the ideXlab platform.
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gaussian networks for direct adaptive control
IEEE Transactions on Neural Networks, 1992Co-Authors: Robert M Sanner, Jeanjacques E SlotineAbstract:A direct adaptive tracking control architecture is proposed and evaluated for a class of continuous-time nonlinear dynamic systems for which an explicit linear parameterization of the uncertainty in the dynamics is either unknown or impossible. The architecture uses a network of Gaussian radial basis functions to adaptively compensate for the plant nonlinearities. Under mild assumptions about the degree of smoothness exhibit by the nonlinear functions, the algorithm is proven to be globally stable, with tracking errors converging to a neighborhood of zero. A constructive procedure is detailed, which directly translates the assumed smoothness properties of the nonlinearities involved into a specification of the network required to represent the plant to a chosen degree of accuracy. A stable weight Adjustment Mechanism is determined using Lyapunov theory. The network construction and performance of the resulting controller are illustrated through simulations with example systems. >
Marco Lanuzza - One of the best experts on this subject based on the ideXlab platform.
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live demo an 88fj 40 mhz 0 4v 0 61pj 1ghz 0 9v dual mode logic 8 8 bit multiplier accumulator with a self Adjustment Mechanism in 28 nm fd soi
International Symposium on Circuits and Systems, 2019Co-Authors: Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander FishAbstract:The unique ability of dual mode logic (DML) to self-adapt to computational needs by providing high speed and/or low energy consumption is demonstrated for the first time by silicon measurements in 28nm FD-SOI. At the gate level, the DML design offers the possibility to operate either in the static mode to save energy, or in the dynamic mode to increase speed albeit with higher delay or energy consumption, respectively. In this demonstration, the two operational modes are dynamically managed by a self-Adjustment Mechanism to increase speed or reduce energy of the design at run-time. As a test case a two-stage pipelined multiply-accumulate (MAC) circuit was selected to assess the advantages of DML in terms of speed, energy and area as compared to a conventional CMOS design. We show that the self-adjusted DML MAC achieves both a performance boost of up to 92% and 16% less energy consumption than the equivalent standard CMOS implementation. The energy saved can be even greater (−35%) when the low-power (fully static) mode is enabled. In addition, the DML MAC occupies 25% less area.
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an 88 fj 40 mhz 0 4 v 0 61 pj 1 ghz 0 9 v dual mode logic 8 times 8 bit multiplier accumulator with a self Adjustment Mechanism in 28 nm fd soi
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander FishAbstract:The unique ability of dual-mode logic (DML) to self-adapt to computational needs by providing high speed and/or low energy consumption is demonstrated for the first time by silicon measurements in 28-nm fully depleted silicon on insulator. At the gate level, the DML design offers the possibility to operate either in the static mode to save energy or in the dynamic mode to increase speed, albeit with higher delay or energy consumption, respectively. In this paper, these two operational modes of the DML gates are optimally managed by a self-Adjustment Mechanism to increase speed or reduce the energy of gates/blocks in the design at run time. As a test case, a two-stage pipelined multiply–accumulate (MAC) circuit was selected to assess the advantages of DML in terms of speed, energy, and area as compared to a conventional CMOS design. We show that the self-adjusted DML MAC achieves both a performance boost of up to 92% and 16% less energy consumption than the equivalent standard CMOS implementation. The energy saved can be even greater (up to 35%) when the low-power (fully static) mode is enabled. In addition, the DML MAC occupies 25% less area.
Itamar Levi - One of the best experts on this subject based on the ideXlab platform.
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live demo an 88fj 40 mhz 0 4v 0 61pj 1ghz 0 9v dual mode logic 8 8 bit multiplier accumulator with a self Adjustment Mechanism in 28 nm fd soi
International Symposium on Circuits and Systems, 2019Co-Authors: Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander FishAbstract:The unique ability of dual mode logic (DML) to self-adapt to computational needs by providing high speed and/or low energy consumption is demonstrated for the first time by silicon measurements in 28nm FD-SOI. At the gate level, the DML design offers the possibility to operate either in the static mode to save energy, or in the dynamic mode to increase speed albeit with higher delay or energy consumption, respectively. In this demonstration, the two operational modes are dynamically managed by a self-Adjustment Mechanism to increase speed or reduce energy of the design at run-time. As a test case a two-stage pipelined multiply-accumulate (MAC) circuit was selected to assess the advantages of DML in terms of speed, energy and area as compared to a conventional CMOS design. We show that the self-adjusted DML MAC achieves both a performance boost of up to 92% and 16% less energy consumption than the equivalent standard CMOS implementation. The energy saved can be even greater (−35%) when the low-power (fully static) mode is enabled. In addition, the DML MAC occupies 25% less area.
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an 88 fj 40 mhz 0 4 v 0 61 pj 1 ghz 0 9 v dual mode logic 8 times 8 bit multiplier accumulator with a self Adjustment Mechanism in 28 nm fd soi
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander FishAbstract:The unique ability of dual-mode logic (DML) to self-adapt to computational needs by providing high speed and/or low energy consumption is demonstrated for the first time by silicon measurements in 28-nm fully depleted silicon on insulator. At the gate level, the DML design offers the possibility to operate either in the static mode to save energy or in the dynamic mode to increase speed, albeit with higher delay or energy consumption, respectively. In this paper, these two operational modes of the DML gates are optimally managed by a self-Adjustment Mechanism to increase speed or reduce the energy of gates/blocks in the design at run time. As a test case, a two-stage pipelined multiply–accumulate (MAC) circuit was selected to assess the advantages of DML in terms of speed, energy, and area as compared to a conventional CMOS design. We show that the self-adjusted DML MAC achieves both a performance boost of up to 92% and 16% less energy consumption than the equivalent standard CMOS implementation. The energy saved can be even greater (up to 35%) when the low-power (fully static) mode is enabled. In addition, the DML MAC occupies 25% less area.