The Experts below are selected from a list of 165 Experts worldwide ranked by ideXlab platform

Sungju Park - One of the best experts on this subject based on the ideXlab platform.

  • An Efficient SoC Test Technique by Reusing On/Off-Chip bus Bridge
    2014
    Co-Authors: Jaehoon Song, Juhee Han, Student Member, Sungju Park
    Abstract:

    Abstract—Today’s system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-in-terconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efficient functional and structural testing. The testing time can be significantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional- and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges. Index Terms—advanced microcontroller bus architecture (AMBA), bus bridge, peripheral component interconnect (PCI), system-on-a-chip (SoC), test time, testability. I

  • An Efficient SoC Test Technique by Reusing On/Off-Chip bus Bridge
    IEEE Transactions on Circuits and Systems, 2009
    Co-Authors: Jaehoon Song, Juhee Han, Hyunbean Yi, Sungju Park
    Abstract:

    Today's system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-interconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efficient functional and structural testing. The testing time can be significantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional- and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges.

  • Exploiting an On/off-Chip bus Bridge for an Efficiently Testable SoC
    Journal of the Institute of Electronics Engineers of Korea, 2008
    Co-Authors: Jaehoon Song, Juhee Han, Byeongjin Kim, Hye-ran Jeong, Sungju Park
    Abstract:

    Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, we propose an efficient test access mechanism that exploits an on/off-chip bus bridge for the advanced high-performance bus (AHB) and Peripheral Component Interconnect (PCI) bus. The test application time is considerably reduced by providing dedicated test stimuli input paths and response output paths, and by excluding the bus direction tumaround delays. Experimental results show that area overhead and testing times are considerably reduced in both functional and structural test modes. The proposed technique can be a lied to the other types of on/off-chip bus bridges.

  • for Efficient Test Access to AMBA-based SoC
    2007
    Co-Authors: Jaehoon Song, Juhee Han, Dooyoung Kim, Sungju Park
    Abstract:

    This paper introduces an efficient test access mechanism for advanced Microcontroller bus Architecture (AMBA) based SoC to reduce the test application time while minimally adding a new test interface logic. Testable design technique is applied to an SoC with the advanced high-performance bus (AHB) and PCI bus bridge by maximally reusing the bridge functions. Testing time can be significantly reduced by increasing the test channels and by shortening the test control protocols. Experimental results show that area overhead and testing times in both functional and structural test modes are considerably reduced.

  • Design Reuse of on/off-Chip bus Bridge for Efficient Test Access to AMBA-based SoC
    16th Asian Test Symposium (ATS 2007), 2007
    Co-Authors: Jaehoon Song, Juhee Han, Dooyoung Kim, Sungju Park
    Abstract:

    This paper introduces an efficient test access mechanism for advanced microcontroller bus architecture (AMBA) based SoC to reduce the test application time while minimally adding a new test interface logic. Testable design technique is applied to an SoC with the advanced high-performance bus (AHB) and PCI bus bridge by maximally reusing the bridge functions. Testing time can be significantly reduced by increasing the test channels and by shortening the test control protocols. Experimental results show that area overhead and testing times in both functional and structural test modes are considerably reduced.

Jaehoon Song - One of the best experts on this subject based on the ideXlab platform.

  • An Efficient SoC Test Technique by Reusing On/Off-Chip bus Bridge
    2014
    Co-Authors: Jaehoon Song, Juhee Han, Student Member, Sungju Park
    Abstract:

    Abstract—Today’s system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-in-terconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efficient functional and structural testing. The testing time can be significantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional- and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges. Index Terms—advanced microcontroller bus architecture (AMBA), bus bridge, peripheral component interconnect (PCI), system-on-a-chip (SoC), test time, testability. I

  • An Efficient SoC Test Technique by Reusing On/Off-Chip bus Bridge
    IEEE Transactions on Circuits and Systems, 2009
    Co-Authors: Jaehoon Song, Juhee Han, Hyunbean Yi, Sungju Park
    Abstract:

    Today's system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-interconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efficient functional and structural testing. The testing time can be significantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional- and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges.

  • Exploiting an On/off-Chip bus Bridge for an Efficiently Testable SoC
    Journal of the Institute of Electronics Engineers of Korea, 2008
    Co-Authors: Jaehoon Song, Juhee Han, Byeongjin Kim, Hye-ran Jeong, Sungju Park
    Abstract:

    Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, we propose an efficient test access mechanism that exploits an on/off-chip bus bridge for the advanced high-performance bus (AHB) and Peripheral Component Interconnect (PCI) bus. The test application time is considerably reduced by providing dedicated test stimuli input paths and response output paths, and by excluding the bus direction tumaround delays. Experimental results show that area overhead and testing times are considerably reduced in both functional and structural test modes. The proposed technique can be a lied to the other types of on/off-chip bus bridges.

  • for Efficient Test Access to AMBA-based SoC
    2007
    Co-Authors: Jaehoon Song, Juhee Han, Dooyoung Kim, Sungju Park
    Abstract:

    This paper introduces an efficient test access mechanism for advanced Microcontroller bus Architecture (AMBA) based SoC to reduce the test application time while minimally adding a new test interface logic. Testable design technique is applied to an SoC with the advanced high-performance bus (AHB) and PCI bus bridge by maximally reusing the bridge functions. Testing time can be significantly reduced by increasing the test channels and by shortening the test control protocols. Experimental results show that area overhead and testing times in both functional and structural test modes are considerably reduced.

  • Design Reuse of on/off-Chip bus Bridge for Efficient Test Access to AMBA-based SoC
    16th Asian Test Symposium (ATS 2007), 2007
    Co-Authors: Jaehoon Song, Juhee Han, Dooyoung Kim, Sungju Park
    Abstract:

    This paper introduces an efficient test access mechanism for advanced microcontroller bus architecture (AMBA) based SoC to reduce the test application time while minimally adding a new test interface logic. Testable design technique is applied to an SoC with the advanced high-performance bus (AHB) and PCI bus bridge by maximally reusing the bridge functions. Testing time can be significantly reduced by increasing the test channels and by shortening the test control protocols. Experimental results show that area overhead and testing times in both functional and structural test modes are considerably reduced.

Juhee Han - One of the best experts on this subject based on the ideXlab platform.

  • An Efficient SoC Test Technique by Reusing On/Off-Chip bus Bridge
    2014
    Co-Authors: Jaehoon Song, Juhee Han, Student Member, Sungju Park
    Abstract:

    Abstract—Today’s system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-in-terconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efficient functional and structural testing. The testing time can be significantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional- and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges. Index Terms—advanced microcontroller bus architecture (AMBA), bus bridge, peripheral component interconnect (PCI), system-on-a-chip (SoC), test time, testability. I

  • An Efficient SoC Test Technique by Reusing On/Off-Chip bus Bridge
    IEEE Transactions on Circuits and Systems, 2009
    Co-Authors: Jaehoon Song, Juhee Han, Hyunbean Yi, Sungju Park
    Abstract:

    Today's system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-interconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efficient functional and structural testing. The testing time can be significantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional- and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges.

  • Exploiting an On/off-Chip bus Bridge for an Efficiently Testable SoC
    Journal of the Institute of Electronics Engineers of Korea, 2008
    Co-Authors: Jaehoon Song, Juhee Han, Byeongjin Kim, Hye-ran Jeong, Sungju Park
    Abstract:

    Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, we propose an efficient test access mechanism that exploits an on/off-chip bus bridge for the advanced high-performance bus (AHB) and Peripheral Component Interconnect (PCI) bus. The test application time is considerably reduced by providing dedicated test stimuli input paths and response output paths, and by excluding the bus direction tumaround delays. Experimental results show that area overhead and testing times are considerably reduced in both functional and structural test modes. The proposed technique can be a lied to the other types of on/off-chip bus bridges.

  • for Efficient Test Access to AMBA-based SoC
    2007
    Co-Authors: Jaehoon Song, Juhee Han, Dooyoung Kim, Sungju Park
    Abstract:

    This paper introduces an efficient test access mechanism for advanced Microcontroller bus Architecture (AMBA) based SoC to reduce the test application time while minimally adding a new test interface logic. Testable design technique is applied to an SoC with the advanced high-performance bus (AHB) and PCI bus bridge by maximally reusing the bridge functions. Testing time can be significantly reduced by increasing the test channels and by shortening the test control protocols. Experimental results show that area overhead and testing times in both functional and structural test modes are considerably reduced.

  • Design Reuse of on/off-Chip bus Bridge for Efficient Test Access to AMBA-based SoC
    16th Asian Test Symposium (ATS 2007), 2007
    Co-Authors: Jaehoon Song, Juhee Han, Dooyoung Kim, Sungju Park
    Abstract:

    This paper introduces an efficient test access mechanism for advanced microcontroller bus architecture (AMBA) based SoC to reduce the test application time while minimally adding a new test interface logic. Testable design technique is applied to an SoC with the advanced high-performance bus (AHB) and PCI bus bridge by maximally reusing the bridge functions. Testing time can be significantly reduced by increasing the test channels and by shortening the test control protocols. Experimental results show that area overhead and testing times in both functional and structural test modes are considerably reduced.

Hyunbean Yi - One of the best experts on this subject based on the ideXlab platform.

  • An Efficient SoC Test Technique by Reusing On/Off-Chip bus Bridge
    IEEE Transactions on Circuits and Systems, 2009
    Co-Authors: Jaehoon Song, Juhee Han, Hyunbean Yi, Sungju Park
    Abstract:

    Today's system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-interconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efficient functional and structural testing. The testing time can be significantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional- and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges.

Rainer Dömer - One of the best experts on this subject based on the ideXlab platform.

  • Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
    ACM Transactions on Embedded Computing Systems, 2008
    Co-Authors: Gunar Schirner, Rainer Dömer
    Abstract:

    The increasing complexity of embedded systems requires modeling at higher levels of abstraction. Transaction level modeling (TLM) has been proposed to abstract communication for high-speed system simulation and rapid design space exploration. Although being widely accepted for its high performance and efficiency, TLM often exhibits a significant loss in model accuracy. In this article, we systematically analyze and quantify the speed/accuracy trade-off in TLM. To this end, we provide a classification of TLM abstraction levels based on model granularity and define appropriate metrics and test setups to quantitatively measure and compare the performance and accuracy of such models. Addressing several classes of embedded communication protocols, we apply our analysis to three common bus architectures, the industry-standard AMBA advanced high-performance bus (AHB) as an on-chip parallel bus, the controller area network (CAN) as an off-chip serial bus, and the Motorola ColdFire Master bus as an example for a custom embedded processor bus. Based on the analysis of these individual busses, we then generalize our results for a broader conclusion. The general TLM trade-off offers gains of up to four orders of magnitude in simulation speed, generally however, at the price of low accuracy. We conclude further that model granularity is the key to efficient TLM abstraction, and we identify conditions for accuracy of abstract models. As a result, this article provides general guidelines that allow the system designer to navigate the TLM trade-off effectively and choose the most suitable model for the given application with fast and accurate results.

  • DATE - Quantitative Analysis of Transaction Level Models for the AMBA bus
    Proceedings of the Design Automation & Test in Europe Conference, 2006
    Co-Authors: Gunar Schirner, Rainer Dömer
    Abstract:

    The increasing complexity of embedded systems pushes system designers to higher levels of abstraction. Transaction Level Modeling (TLM) has been proposed to model communication in systems in an abstract manner. Although being widely accepted, TLMs have not been analyzed for their loss in accuracy. This paper will analyze and quantify the speed-accuracy tradeoff of TLM using a case study on AMBA, an industry bus standard. It shows the results of modeling the advanced high-performance bus (AHB) of AMBA using a set of models at different abstraction levels. The analysis of the simulation speed shows improvements of two orders of magnitude for each TLM abstraction, while the timing in the model remains accurate for many applications. As a result, the paper will classify the different models towards their applicability in typical modeling situations, allowing the system designer to achieve fast and accurate simulation of communication.