The Experts below are selected from a list of 1515 Experts worldwide ranked by ideXlab platform
Frank Piessens - One of the best experts on this subject based on the ideXlab platform.
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Temporal Safety for Stack Allocated Memory on Capability Machines
2019 IEEE 32nd Computer Security Foundations Symposium (CSF), 2019Co-Authors: Stelios Tsampas, Dominique Devriese, Frank PiessensAbstract:Memory capabilities as supported in capability machines are very similar to fat pointers, and hence are very useful for the efficient enforcement of spatial Memory safety. Enforcing temporal Memory safety however, is more challenging. This paper investigates an approach to enforce temporal Memory safety for stack-Allocated Memory in C-like languages by extending capabilities with a simple dynamic mechanism. This mechanism ensures that capabilities with a certain lifetime can only be stored in Memory that has a longer lifetime. Our mechanism prevents temporal Memory safety violations, yet is sufficiently permissive to allow typical C coding idioms where addresses of local variables are passed up the call stack. We formalize the desired behavior of a simple C-like language as a dependently typed operational semantics, and we show that existing compilers to capability machines do not simulate this desired behavior: they either have to break temporal safety, or they have to defensively rule out allowed behaviors. Finally, we show that with our proposed dynamic mechanism, our compiler is fully abstract.
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CSF - Temporal Safety for Stack Allocated Memory on Capability Machines
Cell Structure and Function, 2019Co-Authors: Stelios Tsampas, Dominique Devriese, Frank PiessensAbstract:Memory capabilities as supported in capability machines are very similar to fat pointers, and hence are very useful for the efficient enforcement of spatial Memory safety. Enforcing temporal Memory safety however, is more challenging. This paper investigates an approach to enforce temporal Memory safety for stack-Allocated Memory in C-like languages by extending capabilities with a simple dynamic mechanism. This mechanism ensures that capabilities with a certain lifetime can only be stored in Memory that has a longer lifetime. Our mechanism prevents temporal Memory safety violations, yet is sufficiently permissive to allow typical C coding idioms where addresses of local variables are passed up the call stack. We formalize the desired behavior of a simple C-like language as a dependently typed operational semantics, and we show that existing compilers to capability machines do not simulate this desired behavior: they either have to break temporal safety, or they have to defensively rule out allowed behaviors. Finally, we show that with our proposed dynamic mechanism, our compiler is fully abstract.
Lei Wang - One of the best experts on this subject based on the ideXlab platform.
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Exploiting Memory Soft Redundancy for Joint Improvement of Error Tolerance and Access Efficiency
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009Co-Authors: Shuo Wang, Lei WangAbstract:Technology roadmap projects nanoscale multibillion- transistor integration in the coming years. However, on-chip Memory becomes increasingly exposed to the dual challenges of device-level reliability degradation and architecture-level performance gap. In this paper, we propose to exploit the inherent Memory soft (transient) redundancy for on-chip Memory design. Due to the mismatch between fixed cache line size and runtime variations in Memory spatial locality, many irrelevant data are fetched into the Memory thereby wasting Memory spaces. The proposed soft-redundancy Allocated Memory detects and utilizes these Memory spaces for jointly achieving efficient Memory access and effective error control. A runtime reconfiguration scheme is also proposed to further enhance the soft-redundancy allocation. Simulation results demonstrate 74.8% average error-control coverage ratio on the SPEC CPU2000 benchmarks with average of 59.5% and 41.3% reduction in Memory miss rate and bandwidth usage, respectively, as compared to the existing Memory techniques. Furthermore, the proposed technique is fully scalable with respect to various Memory configurations.
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Exploiting Soft Redundancy for Error-Resilient On-Chip Memory Design
2006 IEEE ACM International Conference on Computer Aided Design, 2006Co-Authors: Shuo Wang, Lei WangAbstract:Memory design is facing the upcoming challenges due to a combination of technology scaling and higher levels of integration and system complexity. In particular, Memory circuits become vulnerable to transient (soft) errors caused by particle strikes and process spread. In this paper, we propose a new error-tolerance technique referred to as the soft redundancy for on-chip Memory design. Program runtime variations in Memory spatial locality cause wasted Memory spaces occupied by the irrelevant data. The proposed soft-redundancy Allocated Memory exploits these wasted Memory spaces to achieve efficient Memory access and effective error protection in a coherent manner. Simulation results on the SPEC CPU2000 benchmarks demonstrate 73.7% average error protection coverage ratio on the 23 benchmarks, with average of 52% and 48.3% reduction in Memory miss rate and bandwidth requirement, respectively, as compared to the existing techniques
Stelios Tsampas - One of the best experts on this subject based on the ideXlab platform.
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Temporal Safety for Stack Allocated Memory on Capability Machines
2019 IEEE 32nd Computer Security Foundations Symposium (CSF), 2019Co-Authors: Stelios Tsampas, Dominique Devriese, Frank PiessensAbstract:Memory capabilities as supported in capability machines are very similar to fat pointers, and hence are very useful for the efficient enforcement of spatial Memory safety. Enforcing temporal Memory safety however, is more challenging. This paper investigates an approach to enforce temporal Memory safety for stack-Allocated Memory in C-like languages by extending capabilities with a simple dynamic mechanism. This mechanism ensures that capabilities with a certain lifetime can only be stored in Memory that has a longer lifetime. Our mechanism prevents temporal Memory safety violations, yet is sufficiently permissive to allow typical C coding idioms where addresses of local variables are passed up the call stack. We formalize the desired behavior of a simple C-like language as a dependently typed operational semantics, and we show that existing compilers to capability machines do not simulate this desired behavior: they either have to break temporal safety, or they have to defensively rule out allowed behaviors. Finally, we show that with our proposed dynamic mechanism, our compiler is fully abstract.
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CSF - Temporal Safety for Stack Allocated Memory on Capability Machines
Cell Structure and Function, 2019Co-Authors: Stelios Tsampas, Dominique Devriese, Frank PiessensAbstract:Memory capabilities as supported in capability machines are very similar to fat pointers, and hence are very useful for the efficient enforcement of spatial Memory safety. Enforcing temporal Memory safety however, is more challenging. This paper investigates an approach to enforce temporal Memory safety for stack-Allocated Memory in C-like languages by extending capabilities with a simple dynamic mechanism. This mechanism ensures that capabilities with a certain lifetime can only be stored in Memory that has a longer lifetime. Our mechanism prevents temporal Memory safety violations, yet is sufficiently permissive to allow typical C coding idioms where addresses of local variables are passed up the call stack. We formalize the desired behavior of a simple C-like language as a dependently typed operational semantics, and we show that existing compilers to capability machines do not simulate this desired behavior: they either have to break temporal safety, or they have to defensively rule out allowed behaviors. Finally, we show that with our proposed dynamic mechanism, our compiler is fully abstract.
Shuo Wang - One of the best experts on this subject based on the ideXlab platform.
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Exploiting Memory Soft Redundancy for Joint Improvement of Error Tolerance and Access Efficiency
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009Co-Authors: Shuo Wang, Lei WangAbstract:Technology roadmap projects nanoscale multibillion- transistor integration in the coming years. However, on-chip Memory becomes increasingly exposed to the dual challenges of device-level reliability degradation and architecture-level performance gap. In this paper, we propose to exploit the inherent Memory soft (transient) redundancy for on-chip Memory design. Due to the mismatch between fixed cache line size and runtime variations in Memory spatial locality, many irrelevant data are fetched into the Memory thereby wasting Memory spaces. The proposed soft-redundancy Allocated Memory detects and utilizes these Memory spaces for jointly achieving efficient Memory access and effective error control. A runtime reconfiguration scheme is also proposed to further enhance the soft-redundancy allocation. Simulation results demonstrate 74.8% average error-control coverage ratio on the SPEC CPU2000 benchmarks with average of 59.5% and 41.3% reduction in Memory miss rate and bandwidth usage, respectively, as compared to the existing Memory techniques. Furthermore, the proposed technique is fully scalable with respect to various Memory configurations.
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Exploiting Soft Redundancy for Error-Resilient On-Chip Memory Design
2006 IEEE ACM International Conference on Computer Aided Design, 2006Co-Authors: Shuo Wang, Lei WangAbstract:Memory design is facing the upcoming challenges due to a combination of technology scaling and higher levels of integration and system complexity. In particular, Memory circuits become vulnerable to transient (soft) errors caused by particle strikes and process spread. In this paper, we propose a new error-tolerance technique referred to as the soft redundancy for on-chip Memory design. Program runtime variations in Memory spatial locality cause wasted Memory spaces occupied by the irrelevant data. The proposed soft-redundancy Allocated Memory exploits these wasted Memory spaces to achieve efficient Memory access and effective error protection in a coherent manner. Simulation results on the SPEC CPU2000 benchmarks demonstrate 73.7% average error protection coverage ratio on the 23 benchmarks, with average of 52% and 48.3% reduction in Memory miss rate and bandwidth requirement, respectively, as compared to the existing techniques
Rivalino Matias - One of the best experts on this subject based on the ideXlab platform.
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SBESC - An Exploratory Study on Patterns in Dynamic Memory Allocations
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC), 2016Co-Authors: Alexandre Beletti Ferreira, Rivalino Matias, Vinícius Fonseca MacielAbstract:Dynamic Memory allocation is omnipresent in computer programming, which makes its impact on software performance and scalability a major concern. Hence, it is important to understand how real applications allocate Memory dynamically, answering questions like: How frequent are dynamic Memory allocations? What is the distribution of allocation sizes? What is the average allocations' retention time? To answer these and other questions, we analyzed the Memory allocation and deallocation traces from different real applications under their typical workloads, and found consistent allocation patterns. For instance, we observed that small allocations were predominant (in average 85%) in all applications analyzed, as well as short duration allocations that corresponded to 85.06% of all Allocated Memory. These and other findings were contrasted with a previous work towards assessing their external validity.
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An Exploratory Study on Patterns in Dynamic Memory Allocations
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC), 2016Co-Authors: Alexandre Beletti Ferreira, Rivalino Matias, Vinícius Fonseca MacielAbstract:Dynamic Memory allocation is omnipresent in computer programming, which makes its impact on software performance and scalability a major concern. Hence, it is important to understand how real applications allocate Memory dynamically, answering questions like: How frequent are dynamic Memory allocations? What is the distribution of allocation sizes? What is the average allocations' retention time? To answer these and other questions, we analyzed the Memory allocation and deallocation traces from different real applications under their typical workloads, and found consistent allocation patterns. For instance, we observed that small allocations were predominant (in average 85%) in all applications analyzed, as well as short duration allocations that corresponded to 85.06% of all Allocated Memory. These and other findings were contrasted with a previous work towards assessing their external validity.
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Characterization of Dynamic Memory Allocations in Real-World Applications: An Experimental Study
2015 IEEE 23rd International Symposium on Modeling Analysis and Simulation of Computer and Telecommunication Systems, 2015Co-Authors: Diego Costa, Rivalino MatiasAbstract:Dynamic Memory allocation is one of the most ubiquitous operations in computer programs. In order to design effective Memory allocation algorithms, it is a major requirement to understand the most frequent Memory allocation patterns present in modern applications. In this paper, we present an experimental characterization study of dynamic Memory allocations in seven real-world widely used applications. The results show consistent allocation/deallocation patterns present in different applications. Especially, we observe that most of the allocations fitted a well-defined range of block sizes. Also, we found that more than 70% of all dynamically Allocated Memory lasted no more than 0.1 second in the investigated applications. These and other findings of this study are useful for research works planning synthetic workloads related to dynamic Memory allocations.
