The Experts below are selected from a list of 3717 Experts worldwide ranked by ideXlab platform
Dragan Maksimovic - One of the best experts on this subject based on the ideXlab platform.
-
single Comparator based a d converter for output voltage sensing in power factor correction rectifiers
Energy Conversion Congress and Exposition, 2009Co-Authors: Barry Mather, Dragan MaksimovicAbstract:This paper proposes a digital output voltage sensing method for power factor correction (PFC) rectifiers that requires only a single Analog Comparator and a small amount of digital hardware. Using this method a digital estimation of the output error voltage can be obtained at a rate of twice the line frequency (2f line ) without the use of a traditional Analog to digital converter (A/D). The proposed method effectively implements a windowed A/D around the output reference voltage with a window range equal to the magnitude of the ac output voltage ripple. When used in combination with a nonlinear-carrier (NLC) current controller, a power feedforward function is inherently embedded in the operation of the single-Comparator A/D (SCA/D), which simplifies the voltage loop design and reduces voltage loop gain variation due to operating power level. Experimental results are reported comparing load transient responses using the SCA/D or a traditional A/D in a digitally controlled 300W boost PFC.
Barry Mather - One of the best experts on this subject based on the ideXlab platform.
-
single Comparator based a d converter for output voltage sensing in power factor correction rectifiers
Energy Conversion Congress and Exposition, 2009Co-Authors: Barry Mather, Dragan MaksimovicAbstract:This paper proposes a digital output voltage sensing method for power factor correction (PFC) rectifiers that requires only a single Analog Comparator and a small amount of digital hardware. Using this method a digital estimation of the output error voltage can be obtained at a rate of twice the line frequency (2f line ) without the use of a traditional Analog to digital converter (A/D). The proposed method effectively implements a windowed A/D around the output reference voltage with a window range equal to the magnitude of the ac output voltage ripple. When used in combination with a nonlinear-carrier (NLC) current controller, a power feedforward function is inherently embedded in the operation of the single-Comparator A/D (SCA/D), which simplifies the voltage loop design and reduces voltage loop gain variation due to operating power level. Experimental results are reported comparing load transient responses using the SCA/D or a traditional A/D in a digitally controlled 300W boost PFC.
Advanced Risc Architecture - One of the best experts on this subject based on the ideXlab platform.
-
Programmable Flash
2015Co-Authors: Advanced Risc ArchitectureAbstract:● 120 powerful instructions – most single clock cycle execution ● 32 x 8 general purpose working registers ● Fully static operation ● Non-volatile program and data memories ● 2/4/8K byte of in-system programmable program memory flash (Atmel® ATtiny24/44/84) ● Endurance: 10,000 write/erase cycles ● 128/256/512 bytes in-system programmable EEPROM (Atmel ATtiny24/44/84) ● Endurance: 100,000 write/erase cycles ● 128/256/512 bytes internal SRAM (Atmel ATtiny24/44/84) ● Programming lock for self-programming flash program and EEPROM data security ● Peripheral features ● Two Timer/Counters, 8- and 16-bit counters with two PWM channels on both ● 10-bit ADC ● Eight single-ended channels ● 12 differential ADC channel pairs with programmable gain (1x, 20x) ● Temperature measurement ● Programmable watchdog timer with separate on-chip oscillator ● On-chip Analog Comparator ● Universal serial interface ● Special microcontroller features ● debugWIRE on-chip debug system ● In-system programmable via SPI port 8-bit AVR Microcontroller with 2/4/8K Bytes In-Syste
-
8-bit AVR Microcontroller with 2K Bytes In-System Programmable Flash
2015Co-Authors: Advanced Risc ArchitectureAbstract:? 112 powerful instructions – most single clock cycle execution? 16 x 8 general purpose working registers? Fully static operation? Up to 12 MIPS throughput at 12MHz? Non-volatile program and data memories? 2K bytes of in-system programmable flash program memory? 128 bytes internal SRAM? Flash write/erase cycles: 10,000? Data retention: 20 years at 85oC / 100 years at 25oC? Peripheral features? One 8-bit timer/counter with two PWM channels? One 16-bit timer/counter with two PWM channels? 10-bit Analog to digital converter? 8 single-ended channels? Programmable watchdog timer with separate on-chip oscillator? On-chip Analog Comparator? Master/slave SPI serial interface? Slave TWI serial interface? Special microcontroller features? In-system programmable? External and internal interrupt sources? Low power idle, ADC noise reduction, stand-by and power-down modes? Enhanced power-on reset circuit? Internal calibrated oscillator? I/O and packages? 14-pin SOIC/TSSOP: 12 programmable I/O lines? 12-ball WLCSP: 10 programmable I/O lines? 15-ball UFBGA: 12 programmable I/O lines? 20-pad VQFN: 12 programmable I/O lines? Operating voltage:? 1.8 – 5.5V? Programming voltage
Waldemar Jendernalik - One of the best experts on this subject based on the ideXlab platform.
-
An Ultra-Low-Energy Analog Comparator for A/D Converters in CMOS Image Sensors
Circuits Systems and Signal Processing, 2017Co-Authors: Waldemar JendernalikAbstract:This paper proposes a new solution of an ultra-low-energy Analog Comparator, dedicated to slope Analog-to-digital converters (ADC), particularly suited for CMOS image sensors (CISs) featuring a large number of ADCs. For massively parallel imaging arrays, this number may be as high as tens-hundreds of thousands ADCs. As each ADC includes an Analog Comparator, the number of these Comparators in CIS is always high. Detailed analysis shows that power dissipation of a Comparator contributes significantly to a total power consumption of an ADC. Thus, minimization of the Comparator energy consumption during the Analog-to-digital (A/D) conversion of an image frame is crucial for design of CMOS image sensors. Compared to classical dynamic or continuous-time Comparators operating in the slope ADC, under the same bias conditions, the proposed Comparator shows a 2–3 orders of magnitude reduction of the power consumption. In addition, the proposed topology shows a simple and compact layout and does not require a power-down mechanism. The circuit has been simulated in detail for a 0.18- $$\upmu $$ μ m CMOS technology under two different power supply voltages of 1.8 and 1 V. While implemented in a 12-bit slope ADC of a massively parallel CIS, operating at a speed 1000 fps, the energy required for A/D conversion is 0.5 pJ.
Yuncai Wang - One of the best experts on this subject based on the ideXlab platform.
-
All-optical Analog Comparator.
Scientific Reports, 2016Co-Authors: Pu Li, Xiaogang Yi, Dongliang Zhao, Yongpeng Zhao, Yuncai WangAbstract:An Analog Comparator is one of the core units in all-optical Analog-to-digital conversion (AO-ADC) systems, which digitizes different amplitude levels into two levels of logical ‘1’ or ‘0’ by comparing with a defined decision threshold. Although various outstanding photonic ADC approaches have been reported, almost all of them necessitate an electrical Comparator to carry out this binarization. The use of an electrical Comparator is in contradiction to the aim of developing all-optical devices. In this work, we propose a new concept of an all-optical Analog Comparator and numerically demonstrate an implementation based on a quarter-wavelength-shifted distributed feedback laser diode (QWS DFB-LD) with multiple quantum well (MQW) structures. Our results show that the all-optical Comparator is very well suited for true AO-ADCs, enabling the whole digital conversion from an Analog optical signal (continuous-time signal or discrete pulse signal) to a binary representation totally in the optical domain. In particular, this all-optical Analog Comparator possesses a low threshold power (several mW), high extinction ratio (up to 40 dB), fast operation rate (of the order of tens of Gb/s) and a step-like transfer function.