The Experts below are selected from a list of 73104 Experts worldwide ranked by ideXlab platform
Vern L. Schramm - One of the best experts on this subject based on the ideXlab platform.
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enzymatic transition states and transition state Analog Design
Annual Review of Biochemistry, 1998Co-Authors: Vern L. SchrammAbstract:All chemical transformations pass through an unstable structure called the transition state, which is poised between the chemical structures of the substrates and products. The transition states for chemical reactions are proposed to have lifetimes near 10(-13) sec, the time for a single bond vibration. No physical or spectroscopic method is available to directly observe the structure of the transition state for enzymatic reactions. Yet transition state structure is central to understanding catalysis, because enzymes function by lowering activation energy. An accepted view of enzymatic catalysis is tight binding to the unstable transition state structure. Transition state mimics bind tightly to enzymes by capturing a fraction of the binding energy for the transition state species. The identification of numerous transition state inhibitors supports the transition state stabilization hypothesis for enzymatic catalysis. Advances in methods for measuring and interpreting kinetic isotope effects and advances in computational chemistry have provided an experimental route to understand transition state structure. Systematic analysis of intrinsic kinetic isotope effects provides geometric and electronic structure for enzyme-bound transition states. This information has been used to compare transition states for chemical and enzymatic reactions; determine whether enzymatic activators alter transition state structure; Design transition state inhibitors; and provide the basis for predicting the affinity of enzymatic inhibitors. Enzymatic transition states provide an understanding of catalysis and permit the Design of transition state inhibitors. This article reviews transition state theory for enzymatic reactions. Selected examples of enzymatic transition states are compared to the respective transition state inhibitors.
Z.m. Kovacs-vajna - One of the best experts on this subject based on the ideXlab platform.
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Automatic Scaling Procedures for Analog Design Reuse
IEEE Transactions on Circuits and Systems I: Regular Papers, 2006Co-Authors: A. Savio, Luigi Colalongo, M. Quarantelli, Z.m. Kovacs-vajnaAbstract:In this paper, a methodology for Analog Design reuse is proposed. The basic idea is to keep the circuit topology unchanged while automatically modifying the MOSFETs aspect ratio in order to control the transistor transconductances gm and output conductances gDS. If gm's and gDS's of each transistor are kept unchanged through the scaling procedure, we show that the overall frequency behavior of the scaled circuit remains very similar to the original one. The approach is very simple and it is suitable for the scaling of Analog circuits. No input and output terminals have to be defined and it can be straightforwardly implemented in an automatic scaling tool. When this approach fails, more complex iterative numerical loops may be adopted. In order to validate and compare the scaling approaches, several linear and nonlinear circuits were scaled from a 0.25-mum, 2.5-V voltage supply to a 0.15-mum, 1.2-V voltage supply in standard CMOS technologies
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ISCAS (5) - Scaling rules and parameter tuning procedure for Analog Design reuse in technology migration
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 1Co-Authors: A. Savio, Luigi Colalongo, Z.m. Kovacs-vajna, M. QuarantelliAbstract:In this paper a methodology for Analog Design reuse during technology scaling is proposed. First of all, analytical resizing rules are derived for MOS transistors working in saturation and triode regions. These rules, however, do not account for parasitic effects that, especially in submicron technologies, lead to inaccurate scaling. For this reason, for example, DC gain and unity gain frequency may substantially differ from the original. In order to compensate these inaccuracies, a tuning procedure based on SPICE simulations is proposed. Finally, the migration and tuning procedures are validated and simulation results are compared scaling down a Miller OTA from 0.25 /spl mu/m to 0.15 /spl mu/m technology.
Wan-ju Chiang - One of the best experts on this subject based on the ideXlab platform.
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ICCAD - Performance-centering optimization for system-level Analog Design exploration
ICCAD-2005. IEEE ACM International Conference on Computer-Aided Design 2005., 1Co-Authors: Jian Wang, Larry Pileggi, Tun-shih Chen, Wan-ju ChiangAbstract:In this paper we propose a novel Analog Design optimization methodology to address two key aspects of top-down system-level Design: (1) how to optimally compare and select Analog system architectures in the early phases of Design; and (2) how to hierarchically propagate performance specifications from system level to circuit level to enable independent circuit block Design. Importantly, due to the inaccuracy of early-stage system-level models, and the increasing magnitude of process and environmental variations, the system-level exploration must leave sufficient Design margin to ensure a successful late-stage implementation. Therefore, instead of minimizing a Design objective function, and thereby converging on a constraint boundary, we apply a novel performance centering optimization. Our proposed methodology centers the Analog Design in the performance space, and maximizes the distance to all constraint boundaries. We demonstrate that this early-stage Design margin, which is measured by the volume of the inscribed ellipsoid lying inside the performance constraints, provides an excellent quality measure for comparing different system architectures. The efficacy of our performance centering approach is shown for Analog Design examples, including a complete clock data recovery system Design and implementation.
A. Savio - One of the best experts on this subject based on the ideXlab platform.
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Automatic Scaling Procedures for Analog Design Reuse
IEEE Transactions on Circuits and Systems I: Regular Papers, 2006Co-Authors: A. Savio, Luigi Colalongo, M. Quarantelli, Z.m. Kovacs-vajnaAbstract:In this paper, a methodology for Analog Design reuse is proposed. The basic idea is to keep the circuit topology unchanged while automatically modifying the MOSFETs aspect ratio in order to control the transistor transconductances gm and output conductances gDS. If gm's and gDS's of each transistor are kept unchanged through the scaling procedure, we show that the overall frequency behavior of the scaled circuit remains very similar to the original one. The approach is very simple and it is suitable for the scaling of Analog circuits. No input and output terminals have to be defined and it can be straightforwardly implemented in an automatic scaling tool. When this approach fails, more complex iterative numerical loops may be adopted. In order to validate and compare the scaling approaches, several linear and nonlinear circuits were scaled from a 0.25-mum, 2.5-V voltage supply to a 0.15-mum, 1.2-V voltage supply in standard CMOS technologies
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ISCAS (5) - Scaling rules and parameter tuning procedure for Analog Design reuse in technology migration
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 1Co-Authors: A. Savio, Luigi Colalongo, Z.m. Kovacs-vajna, M. QuarantelliAbstract:In this paper a methodology for Analog Design reuse during technology scaling is proposed. First of all, analytical resizing rules are derived for MOS transistors working in saturation and triode regions. These rules, however, do not account for parasitic effects that, especially in submicron technologies, lead to inaccurate scaling. For this reason, for example, DC gain and unity gain frequency may substantially differ from the original. In order to compensate these inaccuracies, a tuning procedure based on SPICE simulations is proposed. Finally, the migration and tuning procedures are validated and simulation results are compared scaling down a Miller OTA from 0.25 /spl mu/m to 0.15 /spl mu/m technology.
M. Quarantelli - One of the best experts on this subject based on the ideXlab platform.
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Automatic Scaling Procedures for Analog Design Reuse
IEEE Transactions on Circuits and Systems I: Regular Papers, 2006Co-Authors: A. Savio, Luigi Colalongo, M. Quarantelli, Z.m. Kovacs-vajnaAbstract:In this paper, a methodology for Analog Design reuse is proposed. The basic idea is to keep the circuit topology unchanged while automatically modifying the MOSFETs aspect ratio in order to control the transistor transconductances gm and output conductances gDS. If gm's and gDS's of each transistor are kept unchanged through the scaling procedure, we show that the overall frequency behavior of the scaled circuit remains very similar to the original one. The approach is very simple and it is suitable for the scaling of Analog circuits. No input and output terminals have to be defined and it can be straightforwardly implemented in an automatic scaling tool. When this approach fails, more complex iterative numerical loops may be adopted. In order to validate and compare the scaling approaches, several linear and nonlinear circuits were scaled from a 0.25-mum, 2.5-V voltage supply to a 0.15-mum, 1.2-V voltage supply in standard CMOS technologies
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ISCAS (5) - Scaling rules and parameter tuning procedure for Analog Design reuse in technology migration
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 1Co-Authors: A. Savio, Luigi Colalongo, Z.m. Kovacs-vajna, M. QuarantelliAbstract:In this paper a methodology for Analog Design reuse during technology scaling is proposed. First of all, analytical resizing rules are derived for MOS transistors working in saturation and triode regions. These rules, however, do not account for parasitic effects that, especially in submicron technologies, lead to inaccurate scaling. For this reason, for example, DC gain and unity gain frequency may substantially differ from the original. In order to compensate these inaccuracies, a tuning procedure based on SPICE simulations is proposed. Finally, the migration and tuning procedures are validated and simulation results are compared scaling down a Miller OTA from 0.25 /spl mu/m to 0.15 /spl mu/m technology.
