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Analog Digital Converter

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M J W Rodwell – One of the best experts on this subject based on the ideXlab platform.

  • an 18 ghz continuous time spl sigma spl delta Analog Digital Converter implemented in inp transferred substrate hbt technology
    IEEE Journal of Solid-state Circuits, 2001
    Co-Authors: S Jaganathan, S Krishnan, D Mensa, T Mathew, Y Betser, Yun Wei, D Scott, R Urteaga, M J W Rodwell
    Abstract:

    We report an 18-GHz clock-rate second-order continuous-time /spl Sigma/-/spl Delta/ AnalogDigital Converter (ADC) implemented using InP-transferred substrate HBTs. Under two-tone test conditions, the ADC achieved 43 dB and 33 dB SNR at signal frequencies of 500 MHz and 990 MHz, respectively. The IC occupied 1.95 mm/sup 2/ die area and dissipated /spl sim/1.5 W.

  • An 8-GHz continuous-time /spl Sigma/-/spl Delta/ AnalogDigital Converter in an InP-based DHBT technology
    IEEE MTT-S International Microwave Symposium Digest 2003, 1
    Co-Authors: S Krishnan, Yun Wei, D Scott, Miguel Urteaga, Z. Griffith, Mattias E. Dahlstrom, N. Parthasarathy, M J W Rodwell
    Abstract:

    We report an 8-GHz clock-rate, second-order continuous-time /spl Sigma/-/spl Delta/ AnalogDigital Converter (ADC) that achieves 57.4-, 51.7-, and 40.2-dB SNR at signal sampling rates of 125, 250, and 500 Ms/s, respectively. The integrated circuit occupied 1.45-mm/sup 2/ die area, contains 76 transistors, is fabricated in an InP-based HBT technology, and dissipates /spl sim/1.8 W. We also study the effect of excess delay on modulator performance, and show that excess delay does not affect performance as long as the centroid-in-time of the DigitalAnalog Converter pulse remains stationary.

S Krishnan – One of the best experts on this subject based on the ideXlab platform.

  • an 18 ghz continuous time spl sigma spl delta Analog Digital Converter implemented in inp transferred substrate hbt technology
    IEEE Journal of Solid-state Circuits, 2001
    Co-Authors: S Jaganathan, S Krishnan, D Mensa, T Mathew, Y Betser, Yun Wei, D Scott, R Urteaga, M J W Rodwell
    Abstract:

    We report an 18-GHz clock-rate second-order continuous-time /spl Sigma/-/spl Delta/ AnalogDigital Converter (ADC) implemented using InP-transferred substrate HBTs. Under two-tone test conditions, the ADC achieved 43 dB and 33 dB SNR at signal frequencies of 500 MHz and 990 MHz, respectively. The IC occupied 1.95 mm/sup 2/ die area and dissipated /spl sim/1.5 W.

  • An 8-GHz continuous-time /spl Sigma/-/spl Delta/ AnalogDigital Converter in an InP-based DHBT technology
    IEEE MTT-S International Microwave Symposium Digest 2003, 1
    Co-Authors: S Krishnan, Yun Wei, D Scott, Miguel Urteaga, Z. Griffith, Mattias E. Dahlstrom, N. Parthasarathy, M J W Rodwell
    Abstract:

    We report an 8-GHz clock-rate, second-order continuous-time /spl Sigma/-/spl Delta/ AnalogDigital Converter (ADC) that achieves 57.4-, 51.7-, and 40.2-dB SNR at signal sampling rates of 125, 250, and 500 Ms/s, respectively. The integrated circuit occupied 1.45-mm/sup 2/ die area, contains 76 transistors, is fabricated in an InP-based HBT technology, and dissipates /spl sim/1.8 W. We also study the effect of excess delay on modulator performance, and show that excess delay does not affect performance as long as the centroid-in-time of the DigitalAnalog Converter pulse remains stationary.

S Jaganathan – One of the best experts on this subject based on the ideXlab platform.

  • an 18 ghz continuous time spl sigma spl delta Analog Digital Converter implemented in inp transferred substrate hbt technology
    IEEE Journal of Solid-state Circuits, 2001
    Co-Authors: S Jaganathan, S Krishnan, D Mensa, T Mathew, Y Betser, Yun Wei, D Scott, R Urteaga, M J W Rodwell
    Abstract:

    We report an 18-GHz clock-rate second-order continuous-time /spl Sigma/-/spl Delta/ AnalogDigital Converter (ADC) implemented using InP-transferred substrate HBTs. Under two-tone test conditions, the ADC achieved 43 dB and 33 dB SNR at signal frequencies of 500 MHz and 990 MHz, respectively. The IC occupied 1.95 mm/sup 2/ die area and dissipated /spl sim/1.5 W.

D Scott – One of the best experts on this subject based on the ideXlab platform.

  • an 18 ghz continuous time spl sigma spl delta Analog Digital Converter implemented in inp transferred substrate hbt technology
    IEEE Journal of Solid-state Circuits, 2001
    Co-Authors: S Jaganathan, S Krishnan, D Mensa, T Mathew, Y Betser, Yun Wei, D Scott, R Urteaga, M J W Rodwell
    Abstract:

    We report an 18-GHz clock-rate second-order continuous-time /spl Sigma/-/spl Delta/ AnalogDigital Converter (ADC) implemented using InP-transferred substrate HBTs. Under two-tone test conditions, the ADC achieved 43 dB and 33 dB SNR at signal frequencies of 500 MHz and 990 MHz, respectively. The IC occupied 1.95 mm/sup 2/ die area and dissipated /spl sim/1.5 W.

  • An 8-GHz continuous-time /spl Sigma/-/spl Delta/ AnalogDigital Converter in an InP-based DHBT technology
    IEEE MTT-S International Microwave Symposium Digest 2003, 1
    Co-Authors: S Krishnan, Yun Wei, D Scott, Miguel Urteaga, Z. Griffith, Mattias E. Dahlstrom, N. Parthasarathy, M J W Rodwell
    Abstract:

    We report an 8-GHz clock-rate, second-order continuous-time /spl Sigma/-/spl Delta/ AnalogDigital Converter (ADC) that achieves 57.4-, 51.7-, and 40.2-dB SNR at signal sampling rates of 125, 250, and 500 Ms/s, respectively. The integrated circuit occupied 1.45-mm/sup 2/ die area, contains 76 transistors, is fabricated in an InP-based HBT technology, and dissipates /spl sim/1.8 W. We also study the effect of excess delay on modulator performance, and show that excess delay does not affect performance as long as the centroid-in-time of the DigitalAnalog Converter pulse remains stationary.

Yun Wei – One of the best experts on this subject based on the ideXlab platform.

  • an 18 ghz continuous time spl sigma spl delta Analog Digital Converter implemented in inp transferred substrate hbt technology
    IEEE Journal of Solid-state Circuits, 2001
    Co-Authors: S Jaganathan, S Krishnan, D Mensa, T Mathew, Y Betser, Yun Wei, D Scott, R Urteaga, M J W Rodwell
    Abstract:

    We report an 18-GHz clock-rate second-order continuous-time /spl Sigma/-/spl Delta/ AnalogDigital Converter (ADC) implemented using InP-transferred substrate HBTs. Under two-tone test conditions, the ADC achieved 43 dB and 33 dB SNR at signal frequencies of 500 MHz and 990 MHz, respectively. The IC occupied 1.95 mm/sup 2/ die area and dissipated /spl sim/1.5 W.

  • An 8-GHz continuous-time /spl Sigma/-/spl Delta/ AnalogDigital Converter in an InP-based DHBT technology
    IEEE MTT-S International Microwave Symposium Digest 2003, 1
    Co-Authors: S Krishnan, Yun Wei, D Scott, Miguel Urteaga, Z. Griffith, Mattias E. Dahlstrom, N. Parthasarathy, M J W Rodwell
    Abstract:

    We report an 8-GHz clock-rate, second-order continuous-time /spl Sigma/-/spl Delta/ AnalogDigital Converter (ADC) that achieves 57.4-, 51.7-, and 40.2-dB SNR at signal sampling rates of 125, 250, and 500 Ms/s, respectively. The integrated circuit occupied 1.45-mm/sup 2/ die area, contains 76 transistors, is fabricated in an InP-based HBT technology, and dissipates /spl sim/1.8 W. We also study the effect of excess delay on modulator performance, and show that excess delay does not affect performance as long as the centroid-in-time of the DigitalAnalog Converter pulse remains stationary.