The Experts below are selected from a list of 564228 Experts worldwide ranked by ideXlab platform
Hae-seung Lee - One of the best experts on this subject based on the ideXlab platform.
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An NMOS input merged bipolar/sidewall-MOS transistor with a bypass sidewall MOS transistor (NBiBMOS transistor)
IEEE Electron Device Letters, 1992Co-Authors: J.j. Lutsky, R. Reif, Hae-seung LeeAbstract:The concept of merging a vertical n-p-n bipolar and two sidewall NMOS Transistors into an NMOS input merged bipolar/sidewall-MOS transistor with a bypass sidewall NMOS transistor structure (NBiBMOS transistor) is described. The output current of this structure, unlike that of NBiMOS Transistors, is significant even when the output voltage (V/sub CE/ or V/sub DE/) is less than the turn-on voltage of the n-p-n bipolar transistor (V/sub BE/= approximately 0.8 V). This structure, when used in BiCMOS logic gates, will allow the output voltage to swing all the way to 0.0 V rather than to 0.8 V. The feasibility of this concept was demonstrated by fabricating and DC characterizing the NBiBMOS transistor structures, which occupy approximately 1.2 times the area of a single n-p-n bipolar transistor. The NBiBMOS transistor has a higher drive capability than that of a structure consisting of an NBiMOS and a separate bypass transistor, because the body-source junction of the bypass NMOS transistor is forward biased. >
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PMOS input merged bipolar/sidewall MOS Transistors (PBiMOS Transistors)
IEEE Electron Device Letters, 1991Co-Authors: R. Reif, Hae-seung LeeAbstract:A concept of merging vertical n-p-n bipolar and sidewall PMOS Transistors into merged PBiMOS Transistors is described. This concept allows device structures which perform more complex functions to be integrated into a given area. The feasibility of this concept is demonstrated by fabricating and DC characterizing PBiMOS transistor structures which occupy approximately 1.1 times the area of a single n-p-n bipolar transistor. The PMOS sidewall transistor characterization results suggest that a reasonable control of the key device parameters may be achieved. These results also suggest that, for the 23-nm gate oxide thickness, the doping requirements for the n/sup -/ collector of the n-p-n bipolar and the channel of the sidewall PMOS Transistors are similar. >
Ray-hua Horng - One of the best experts on this subject based on the ideXlab platform.
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Thin Film Transistor
Crystals, 2019Co-Authors: Ray-hua HorngAbstract:The special issue is "Thin Film Transistor". There are eight contributed papers. They focus on organic thin film Transistors, fluorinated oligothiophenes Transistors, surface treated or hydrogen effect on oxide-semiconductor-based thin film Transistors, and their corresponding application in flat panel displays and optical detecting. The present special issue on “Thin Film Transistor” can be considered as a status report reviewing the progress that has been made recently on thin film transistor technology. These papers can provide the readers with more research information and corresponding application potential about Thin Film Transistors.
R. Reif - One of the best experts on this subject based on the ideXlab platform.
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An NMOS input merged bipolar/sidewall-MOS transistor with a bypass sidewall MOS transistor (NBiBMOS transistor)
IEEE Electron Device Letters, 1992Co-Authors: J.j. Lutsky, R. Reif, Hae-seung LeeAbstract:The concept of merging a vertical n-p-n bipolar and two sidewall NMOS Transistors into an NMOS input merged bipolar/sidewall-MOS transistor with a bypass sidewall NMOS transistor structure (NBiBMOS transistor) is described. The output current of this structure, unlike that of NBiMOS Transistors, is significant even when the output voltage (V/sub CE/ or V/sub DE/) is less than the turn-on voltage of the n-p-n bipolar transistor (V/sub BE/= approximately 0.8 V). This structure, when used in BiCMOS logic gates, will allow the output voltage to swing all the way to 0.0 V rather than to 0.8 V. The feasibility of this concept was demonstrated by fabricating and DC characterizing the NBiBMOS transistor structures, which occupy approximately 1.2 times the area of a single n-p-n bipolar transistor. The NBiBMOS transistor has a higher drive capability than that of a structure consisting of an NBiMOS and a separate bypass transistor, because the body-source junction of the bypass NMOS transistor is forward biased. >
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PMOS input merged bipolar/sidewall MOS Transistors (PBiMOS Transistors)
IEEE Electron Device Letters, 1991Co-Authors: R. Reif, Hae-seung LeeAbstract:A concept of merging vertical n-p-n bipolar and sidewall PMOS Transistors into merged PBiMOS Transistors is described. This concept allows device structures which perform more complex functions to be integrated into a given area. The feasibility of this concept is demonstrated by fabricating and DC characterizing PBiMOS transistor structures which occupy approximately 1.1 times the area of a single n-p-n bipolar transistor. The PMOS sidewall transistor characterization results suggest that a reasonable control of the key device parameters may be achieved. These results also suggest that, for the 23-nm gate oxide thickness, the doping requirements for the n/sup -/ collector of the n-p-n bipolar and the channel of the sidewall PMOS Transistors are similar. >
R Chau - One of the best experts on this subject based on the ideXlab platform.
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high performance fully depleted tri gate cmos Transistors
IEEE Electron Device Letters, 2003Co-Authors: Brian S Doyle, Suman Datta, Mark Beaverton Doczy, Scott Hareland, B Jin, Jack Portland Kavalieros, Thomas D Linton, Anand Portland Murthy, Rafael Rios, R ChauAbstract:Fully-depleted (FD) tri-gate CMOS Transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The Transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate Transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS Transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate Transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk Transistors in the near future.
Helinda Nominanda - One of the best experts on this subject based on the ideXlab platform.
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nonvolatile hydrogenated amorphous silicon thin film transistor memory devices
Applied Physics Letters, 2006Co-Authors: Helinda NominandaAbstract:The floating gate n-channel amorphous-silicon thin-film transistor nonvolatile memory device, which includes an a-Si:H layer embedded in the SiNx gate dielectric layer, has been prepared and studied. The transistor’s hysteresis of transfer characteristic curves has been used to demonstrate its memory function. A steady threshold voltage change between the “0” and “1” states has been achieved. A large charge retention time of >3600s with the “write” and “erase” gap of 0.5V has been detected. This kind of device brings additional functions to the a-Si:H thin-film Transistors, which can expand its application into various areas.
