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Chris Van Hoof – One of the best experts on this subject based on the ideXlab platform.

  • a 13 mu rm a Analog Signal processing ic for accurate recognition of multiple intra cardiac Signals
    IEEE Transactions on Biomedical Circuits and Systems, 2013
    Co-Authors: Long Yan, Sunyoung Kim, Julia Pettine, Srinjoy Mitra, Dongwoo Jee, Hyejung Kim, Masato Osawa, Yasunari Harada, Kosei Tamiya, Chris Van Hoof
    Abstract:

    A low-power Analog Signal processing IC is presented for the low-power heart rhythm analysis. The ASIC features 3 identical, but independent intra-ECG readout channels each equipping an Analog QRS feature extractor for low-power consumption and fast diagnosis of the fatal case. A 16-level digitized sine-wave synthesizer together with a synchronous readout circuit can measure bio-impedance in the range of 0.1-4.4 kΩ with 33 mΩrms resolution and higher than 97% accuracy. The proposed 25 mm2 ASIC consumes only 13 μA from 2.2 V. It is a highly integrated solution offering all the functionality of acquiring multiple high quality intra-cardiac Signals, requiring only a few limited numbers of external passives.

  • a 30 mu w Analog Signal processor asic for portable biopotential Signal monitoring
    IEEE Journal of Solid-state Circuits, 2011
    Co-Authors: Refet Firat Yazicioglu, Sunyoung Kim, Tom Torfs, Hyejung Kim, Chris Van Hoof
    Abstract:

    This paper presents the design and implementation of an Analog Signal processor (ASP) ASIC for portable ECG monitoring systems. The ASP ASIC performs four major functionalities: 1) ECG Signal extraction with high resolution, 2) ECG Signal feature extraction, 3) adaptive sampling ADC for the compression of ECG Signals, 4) continuous-time electrode-tissue impedance monitoring for Signal integrity monitoring. These functionalities enable the development of wireless ECG monitoring systems that have significantly lower power consumption yet that are more capable than their predecessors. The ASP has been implemented in 0.5 μm CMOS process and consumes 30 μW from a 2 V supply. The noise density of the ECG readout channel is 85 nV/√Hz and the CMRR is better that 105 dB. The adaptive sampling ADC is capable of compressing the ECG data by a factor of 7 and the heterodyne chopper readout extracts the features of the ECG Signals. Combination of these two features leads to a factor 4 reduction in the power consumption of a wireless ECG monitoring system. Furthermore, the proposed continuous-time impedance monitoring circuit enables the monitoring of the Signal integrity.

  • a 30µw Analog Signal processor asic for biomedical Signal monitoring
    International Solid-State Circuits Conference, 2010
    Co-Authors: Refet Firat Yazicioglu, Sunyoung Kim, Tom Torfs, Patrick Merken, Chris Van Hoof
    Abstract:

    Power efficiency of readout circuits for ambulatory monitoring of biopotential Signals has been significantly improved during recent years [1]–[3], leaving digital Signal processing (DSP) and wireless transmission dominating the system power [4]. In addition, field tests have revealed that motion artifacts are a significant problem requiring even more processing power to differentiate between biological information and irrelevant motion artifacts. The presented Analog Signal Processor (ASP) not only addresses the power efficient extraction of ECG Signals, but also improves the state-of-the-art by providing a low-power means for both reducing the data rate of ECG Signals through adaptive sampling and improving the robustness by monitoring motion artifacts. It should be noted that these problems are traditionally being tackled in DSP increasing the system power. Referring to Figure 6.6.1, the ASP consists of an ECG readout channel, two quadrature readout channels for continuous-time (CT) monitoring of electrode-tissue impedance, two quadrature readout channels for tracking power fluctuations in a frequency band, and an activity detector (AD) that can sense the frequency content of the ECG Signal and adapt the sampling rate of the integrated ADC.

Christophe Caloz – One of the best experts on this subject based on the ideXlab platform.

  • Loss-Gain Equalized Reconfigurable C-Section Analog Signal Processor
    IEEE Transactions on Microwave Theory and Techniques, 2017
    Co-Authors: Lianfeng Zou, Shulabh Gupta, Christophe Caloz
    Abstract:

    We present a loss-gain equalized reconfigurable C-section Analog Signal processor (ASP) for dynamic radio Analog Signal processing (R-ASP). Such an ASP provides realtime tunable group delay response with all-pass transmission. We propose a lumped loss-gain implementation, where tuning and equalization are mostly easily achieved. A theoretical study derives the transfer function and the fundamental characteristics of the device. The ASP is finally experimentally demonstrated, first using a single loss-gain pair and finally a three cascaded loss-gain pair structure with full reconfigurability, where up-chirp and down-chirp group delays are shown for illustration. It is expected that this ASP will find wide applications in R-ASP systems requiring dynamic adaptability.

  • Tunable C-section phaser for dynamic Analog Signal processing
    2017 XXXIInd General Assembly and Scientific Symposium of the International Union of Radio Science (URSI GASS), 2017
    Co-Authors: Xiaoyi Wang, Lianfeng Zou, Christophe Caloz
    Abstract:

    This paper proposes a tunable phaser consisting of a conventional C-section incorporating two small-value varactors. Theoretical analysis shows that the varactors add a transmitting pole to the frequency response of the phaser and that this pole addition leads to a wide passband in addition to the group delay tunability provided by the varactors. A proof-of-concconcept design example is provided. Such a tunable phaser is expected to find wide applications in dynamic Real-Time Analog Signal Processing (R-ASP).

  • crlh crlh c section dispersive delay structures with enhanced group delay swing for higher Analog Signal processing resolution
    IEEE Transactions on Microwave Theory and Techniques, 2012
    Co-Authors: Shulabh Gupta, Dimitrios L Sounas, H V Nguyen, Qingfeng Zhang, Christophe Caloz
    Abstract:

    A novel dispersive delay structure (DDS) based on a composite right/left-handed (CRLH)-CRLH coupler is proposed and demonstrated by both full-wave and experimental results. The experimental prototypes are compact and shielded multilayer DDSs implemented in low-temperature co-fired ceramics technology. Compared to the conventional all-pass C-section DDS, the proposed CRLH C-section DDS exhibit a larger group-delay swing, which leads to higher resolution in Analog Signal processing applications, as a result of their higher coupling capability. Moreover, they feature a larger bandwidth and a smaller size. A generalized wave-interference analysis is presented to both rigorously derive the transfer functions and group-delay characteristics of C-section DDSs and provide deeper insight into their operating mechanisms in both their left- and right-handed regimes.

Jian Wang – One of the best experts on this subject based on the ideXlab platform.

  • Experimental demonstration of Analog Signal transmission in a silicon photonic crystal L3 resonator.
    Optics express, 2015
    Co-Authors: Chengcheng Gui, Yong Zhang, Jinsong Xia, Jian Wang
    Abstract:

    We design and fabricate a silicon photonic crystal L3 resonator for chip-scale Analog Signal transmission. The lattice constant (a) is 420 nm, and the radius of holes (r) is 126 nm. The three holes adjacent to the cavity are laterally shifted by 0.175a, 0.025a and 0.175a, respectively. We experimentally evaluate the performance of silicon photonic crystal L3 resonator for chip-scale Analog Signal transmission. The spurious free dynamic ranges (SFDRs) of the second-order harmonic distortion (SHD) and the third-order harmonic distortion (THD), which are important factors to assess the Analog link performance, are measured for the chip-scale Analog Signal transmission through the fabricated silicon photonic crystal L3 resonator. The SHD SFDR and THD SFDR are measured to be ~34.6 dB and ~52.2 dB even with the input optical carrier sitting at the dip resonance wavelength of the fabricated silicon photonic crystal L3 resonator. The influences of the optical carrier wavelength and input optical power on the SHD SFDR and THD SFDR are studied in the experiment. The impacts of geometric parameters of the cavity structure (lattice constant, radius of holes, shift of the hole) on the Analog Signal transmission are also analyzed, showing favorable Analog link performance with relatively large fabrication tolerance to design parameters.

  • Performance evaluation of Analog Signal transmission in an orbital angular momentum multiplexing system
    Optics letters, 2015
    Co-Authors: Jian Wang
    Abstract:

    We propose and experimentally demonstrate Analog Signal transmission in an orbital angular momentum (OAM) multiplexing system. By employing two spatial light modulators (SLMs), each loaded with a complex phase pattern generating 4 OAM beams, an 8 OAM multiplexing system is established for Analog Signal transmissions. The crosstalk between each OAM channel is measured to assess the performance of the OAM multiplexing system. Using 3-GHz Analog Signals over 8 OAM beams, we evaluate the performance of OAM multiplexing Analog Signal transmissions. The spurious free dynamic range (SFDR) of the second-order-harmonic distortion (SHD) and the third-order-harmonic distortion (THD) are measured and characterized for each OAM channel.

  • Experimental performance evaluation of Analog Signal transmission in a photonic crystal ring resonator
    Advanced Photonics for Communications, 2014
    Co-Authors: Chengcheng Gui, Yong Zhang, Jinsong Xia, Jian Wang
    Abstract:

    We experimentally evaluate the performance of on-chip photonic crystal ring resonator for Analog Signal transmission. The transmission performance is evaluated by SFDR. The SHD/THD SFDRs are measured under different wavelengths and optical powers.

Francois Rivet – One of the best experts on this subject based on the ideXlab platform.

  • A Radio-Frequency Real-Time Spectrum Sensor based on an Analog Signal Processing Magnitude Calculator
    , 2017
    Co-Authors: Julien Orlando, Francois Rivet, Yann Deval
    Abstract:

    This paper presents a wideband CMOS FDSOI fully-balanced Analog multiplier which is part of a magnitude calculator for real-time spectrum sensing. Simulations based on a 28nm CMOS FDSOI technology show that the proposed multiplier offers 13.8GHz bandwidth when loaded by a high capacitance with a power consumption of 343uW under a 1V supply. Multiplication between high frequency voltage samples satisfy properties of common multiplication in arithmetic and can be useful in Analog Signal processing such as real-time spectrum sensing.

  • Adaptive interferer cancellation using a Sampled Analog Signal Processor
    , 2014
    Co-Authors: Oskar Holstensson, Francois Rivet, Yann Deval, Nicolas Regimbal, Patrick Garrec, Thierry Taris
    Abstract:

    Software defined radios are developed with the aim to demodulate any standard. However, constraints make this practically unfeasible. A sampled Analog Signal processor was developed performing a fast Fourier transform using voltage samples. The idea is to process any RF Signal 0 to 5 GHz using the fast Fourier transform to obtain frequency shifting and filtering, presenting a new approach to bring software radio closer to reality. A second version of the Analog Signal processor using 65 nm CMOS technology from STMicroelectronics is presented and measured

  • Analog Signal Processing: an hardware solution to achieve Software Radio concept
    , 2012
    Co-Authors: Francois Rivet
    Abstract:

    The multimedia convergence in mobile phones is calling for new RF architectures. The Software Radio concept is claimed to be a solution toward low power, low cost reconfigurable systems. It is characterized by a one chip solution, able to handle any RF standards. It receives any RF Signals in a 0 to 5GHz frequency range. Such a solution is nowadays a dream in the case of handsets. Huge technological constraints remain on Analog to Digital Conversion which has to be brought closer and closer to the antenna. As technical bottlenecks are expected to be unsolved in the next 15 years, disruptive RF receiver architectures are found to address the Software Radio concept. Analog Signal processing is one of the clues of this issue. This presentation will mainly focus on the design of a wide band, low power, and low cost Analog Signal processor. Technological benefits but also drawbacks are exhibited. The question is: can Analog save digital to achieve Software Radio concept ?

Yann Deval – One of the best experts on this subject based on the ideXlab platform.

  • A Radio-Frequency Real-Time Spectrum Sensor based on an Analog Signal Processing Magnitude Calculator
    , 2017
    Co-Authors: Julien Orlando, Francois Rivet, Yann Deval
    Abstract:

    This paper presents a wideband CMOS FDSOI fully-balanced Analog multiplier which is part of a magnitude calculator for real-time spectrum sensing. Simulations based on a 28nm CMOS FDSOI technology show that the proposed multiplier offers 13.8GHz bandwidth when loaded by a high capacitance with a power consumption of 343uW under a 1V supply. Multiplication between high frequency voltage samples satisfy properties of common multiplication in arithmetic and can be useful in Analog Signal processing such as real-time spectrum sensing.

  • Adaptive interferer cancellation using a Sampled Analog Signal Processor
    , 2014
    Co-Authors: Oskar Holstensson, Francois Rivet, Yann Deval, Nicolas Regimbal, Patrick Garrec, Thierry Taris
    Abstract:

    Software defined radios are developed with the aim to demodulate any standard. However, constraints make this practically unfeasible. A sampled Analog Signal processor was developed performing a fast Fourier transform using voltage samples. The idea is to process any RF Signal 0 to 5 GHz using the fast Fourier transform to obtain frequency shifting and filtering, presenting a new approach to bring software radio closer to reality. A second version of the Analog Signal processor using 65 nm CMOS technology from STMicroelectronics is presented and measured

  • A Low-Power 2 GHz Discrete Time Weighting System Dedicated To Sampled Analog Signal Processing
    , 2011
    Co-Authors: Yoann Abiven, Francois Rivet, Yann Deval, Dominique Dallet, Didier Belot, Thierry Taris
    Abstract:

    Multi-standard applications encounter several developments in the wireless systems. A single receiver is required for any standard of communication. Software Radio (SR) is an illustration of this concept. This paper presents a design methodology to ease the design of a flexible RF receiver based on an Analog discrete time Fast Fourier Transform (FFT). A proposed architecture named SASP (Sampled Analog Signal Processor) targets the previously exposed concept for wireless constraints. The FFT algorithm brings an Analog weighting unit which is the most power hungry part in such an Analog discrete time processor.