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Tatsuo Higuchi - One of the best experts on this subject based on the ideXlab platform.
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Arithmetic Circuit Verification Based on Symbolic Computer Algebra
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2008Co-Authors: Yuki Watanabe, Takafumi Aoki, Naofumi Homma, Tatsuo HiguchiAbstract:This paper presents a formal approach to verify Arithmetic Circuits using symbolic computer algebra. Our method describes Arithmetic Circuits directly with high-level mathematical objects based on weighted number systems and Arithmetic formulae. Such Circuit description can be effectively verified by polynomial reduction techniques using Grobner Bases. In this paper, we describe how the symbolic computer algebra can be used to describe and verify Arithmetic Circuits. The advantageous effects of the proposed approach are demonstrated through experimental verification of some Arithmetic Circuits such as multiply-accumulator and FIR filter. The result shows that the proposed approach has a definite possibility of verifying practical Arithmetic Circuits.
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application of symbolic computer algebra to Arithmetic Circuit verification
International Conference on Computer Design, 2007Co-Authors: Yuki Watanabe, Takafumi Aoki, Naofumi Homma, Tatsuo HiguchiAbstract:This paper presents a formal approach to verify Arithmetic Circuits using symbolic computer algebra. Our method describes Arithmetic Circuits directly with high-level mathematical objects based on weighted number systems and Arithmetic formulae. Such Circuit description can be effectively verified by polynomial reduction techniques using Grobner Bases. In this paper, we describe how the symbolic computer algebra can be used to describe and verify Arithmetic Circuits. The advantageous effects of the proposed approach are demonstrated through experimental verification of some Arithmetic Circuits such as multiply-accumulator and FIR filter. The result shows that the proposed approach has a definite possibility of verifying practical Arithmetic Circuits where the conventional techniques failed.
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ICCD - Application of symbolic computer algebra to Arithmetic Circuit verification
2007 25th International Conference on Computer Design, 2007Co-Authors: Yuki Watanabe, Takafumi Aoki, Naofumi Homma, Tatsuo HiguchiAbstract:This paper presents a formal approach to verify Arithmetic Circuits using symbolic computer algebra. Our method describes Arithmetic Circuits directly with high-level mathematical objects based on weighted number systems and Arithmetic formulae. Such Circuit description can be effectively verified by polynomial reduction techniques using Grobner Bases. In this paper, we describe how the symbolic computer algebra can be used to describe and verify Arithmetic Circuits. The advantageous effects of the proposed approach are demonstrated through experimental verification of some Arithmetic Circuits such as multiply-accumulator and FIR filter. The result shows that the proposed approach has a definite possibility of verifying practical Arithmetic Circuits where the conventional techniques failed.
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Evolutionary Synthesis of Arithmetic Circuit Structures
Artificial Intelligence Review, 2003Co-Authors: Takafum Aoki, Naofumi Homma, Tatsuo HiguchiAbstract:This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to Arithmetic Circuit synthesis. Key features of EGG are to employ a graph-based representation of individuals and to manipulate the graph structures directly by evolutionary operations. The potential capability of EGG is demonstrated through experimental synthesis of Arithmetic Circuits with different levels of abstraction. Design examples include (i) combinational multipliers using word-level Arithmetic components (such as parallel counters and parallel shifters), (ii) bit-serial multipliers using bit-level Arithmetic components (such as 1-bit full adders and 1-bit registers), and (iii) multiple-valued current-mode Arithmetic Circuits using transistor-level components (such as current sources and current mirrors).
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evolutionary graph generation system with symbolic verification for Arithmetic Circuit design
Electronics Letters, 2000Co-Authors: Naofumi Homma, Takafumi Aoki, Tatsuo HiguchiAbstract:A novel graph-based evolutionary optimisation technique for Arithmetic Circuit synthesis is proposed. Symbolic verification of the generated Circuit structures is introduced to accelerate the time-consuming evolution process. The evolutionary graph generation (EGG) system based on the proposed technique can successfully generate the optimal 16-bit constant-coefficient multiplier within /spl sim/2.2 h.
Ryan R Williams - One of the best experts on this subject based on the ideXlab platform.
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strong eth breaks with merlin and arthur short non interactive proofs of batch evaluation
Conference on Computational Complexity, 2016Co-Authors: Ryan R WilliamsAbstract:We present an efficient proof system for Multipoint Arithmetic Circuit Evaluation: for any Arithmetic Circuit C(x1, ..., xn) of size s and degree d over a field F, and any inputs a1, ..., aK ∈ Fn. the Prover sends the Verifier the values C(a1), ..., C(aK) ∈ F and a proof of O(K · d) length, and the Verifier tosses poly(log(dK|F|/e)) coins and can check the proof in about O (K · (n+d)+s) time, with probability of error less than e. For small degree d, this "Merlin-Arthur" proof system (a.k.a. MA-proof system) runs in nearly-linear time, and has many applications. For example, we obtain MA-proof systems that run in cn time (for various c < 2) for the Permanent, #Circuit-SAT for all sublinear-depth Circuits, counting Hamiltonian cycles, and infeasibility of 0-1 linear programs. In general, the value of any polynomial in Valiant's class VNP can be certified faster than "exhaustive summation" over all possible assignments. These results strongly refute a Merlin-Arthur Strong ETH and Arthur-Merlin Strong ETH posed by Russell Impagliazzo and others. We also give a three-round (AMA) proof system for quantified Boolean formulas running in 22n/3+o(n) time, nearly-linear time MA-proof systems for counting orthogonal vectors in a collection and finding Closest Pairs in the Hamming metric, and a MA-proof system running in nk/2+O(1)-time for counting k-cliques in graphs. We point to some potential future directions for refuting the Nondeterministic Strong ETH.
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strong eth breaks with merlin and arthur short non interactive proofs of batch evaluation
arXiv: Computational Complexity, 2016Co-Authors: Ryan R WilliamsAbstract:We present an efficient proof system for Multipoint Arithmetic Circuit Evaluation: for every Arithmetic Circuit $C(x_1,\ldots,x_n)$ of size $s$ and degree $d$ over a field ${\mathbb F}$, and any inputs $a_1,\ldots,a_K \in {\mathbb F}^n$, $\bullet$ the Prover sends the Verifier the values $C(a_1), \ldots, C(a_K) \in {\mathbb F}$ and a proof of $\tilde{O}(K \cdot d)$ length, and $\bullet$ the Verifier tosses $\textrm{poly}(\log(dK|{\mathbb F}|/\varepsilon))$ coins and can check the proof in about $\tilde{O}(K \cdot(n + d) + s)$ time, with probability of error less than $\varepsilon$. For small degree $d$, this "Merlin-Arthur" proof system (a.k.a. MA-proof system) runs in nearly-linear time, and has many applications. For example, we obtain MA-proof systems that run in $c^{n}$ time (for various $c < 2$) for the Permanent, $\#$Circuit-SAT for all sublinear-depth Circuits, counting Hamiltonian cycles, and infeasibility of $0$-$1$ linear programs. In general, the value of any polynomial in Valiant's class ${\sf VP}$ can be certified faster than "exhaustive summation" over all possible assignments. These results strongly refute a Merlin-Arthur Strong ETH and Arthur-Merlin Strong ETH posed by Russell Impagliazzo and others. We also give a three-round (AMA) proof system for quantified Boolean formulas running in $2^{2n/3+o(n)}$ time, nearly-linear time MA-proof systems for counting orthogonal vectors in a collection and finding Closest Pairs in the Hamming metric, and a MA-proof system running in $n^{k/2+O(1)}$-time for counting $k$-cliques in graphs. We point to some potential future directions for refuting the Nondeterministic Strong ETH.
Mrinal Kumar - One of the best experts on this subject based on the ideXlab platform.
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On the Power of Border of Depth-3 Arithmetic Circuits
ACM Transactions on Computation Theory, 2020Co-Authors: Mrinal KumarAbstract:We show that over the field of complex numbers, every homogeneous polynomial of degree d can be approximated (in the border complexity sense) by a depth-3 Arithmetic Circuit of top fan-in at most 2. This is quite surprising, since there exist homogeneous polynomials P on n variables of degree 2, such that any depth-3 Arithmetic Circuit computing P must have top fan-in at least Ω (n). As an application, we get a new tradeoff between the top fan-in and formal degree in an approximate analog of the celebrated depth reduction result of Gupta, Kamath, Kayal, and Saptharishi [7, 10]. Formally, we show that if a degree d homogeneous polynomial P can be computed by an Arithmetic Circuit of size s ≥ d, then for every t ≤ d, P is in the border of a depth-3 Circuit of top fan-in sO(t) and formal degree sO(d/t). To the best of our knowledge, the upper bound on the top fan-in in the original proof of Reference [7] is always at least sΩ (√d), regardless of the formal degree.
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unbalancing sets and an almost quadratic lower bound for syntactically multilinear Arithmetic Circuits
Proceedings of the 33rd Computational Complexity Conference on, 2018Co-Authors: Noga Alon, Mrinal Kumar, Ben Lee VolkAbstract:We prove a lower bound of ω(n2/log2 n) on the size of any syntactically multilinear Arithmetic Circuit computing some explicit multilinear polynomial f(x1,...,xn). Our approach expands and improves upon a result of Raz, Shpilka and Yehudayoff ([31]), who proved a lower bound of ω(n4/3/log2 n) for the same polynomial. Our improvement follows from an asymptotically optimal lower bound for a generalized version of Galvin's problem in extremal set theory.
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unbalancing sets and an almost quadratic lower bound for syntactically multilinear Arithmetic Circuits
arXiv e-prints, 2017Co-Authors: Mrinal Kumar, Noga Alon, Ben Lee VolkAbstract:We prove a lower bound of $\Omega(n^2/\log^2 n)$ on the size of any syntactically multilinear Arithmetic Circuit computing some explicit multilinear polynomial $f(x_1, \ldots, x_n)$. Our approach expands and improves upon a result of Raz, Shpilka and Yehudayoff ([RSY08]), who proved a lower bound of $\Omega(n^{4/3}/\log^2 n)$ for the same polynomial. Our improvement follows from an asymptotically optimal lower bound for a generalized version of Galvin's problem in extremal set theory.
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ICALP (1) - Superpolynomial lower bounds for general homogeneous depth 4 Arithmetic Circuits
Automata Languages and Programming, 2014Co-Authors: Mrinal Kumar, Shubhangi SarafAbstract:In this paper, we prove superpolynomial lower bounds for the class of homogeneous depth 4 Arithmetic Circuits. We give an explicit polynomial in VNP of degree n in n 2 variables such that any homogeneous depth 4 Arithmetic Circuit computing it must have size n Ω(loglogn).
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Arithmetic Circuit lower bounds via maxrank
Electronic Colloquium on Computational Complexity, 2013Co-Authors: Mrinal Kumar, Gaurav Maheshwari, Jayalal SarmaAbstract:We introduce the polynomial coefficient matrix and identify maximum rank of this matrix under variable substitution as a complexity measure for multivariate polynomials. We use our techniques to prove super-polynomial lower bounds against several classes of non-multilinear Arithmetic Circuits. In particular, we obtain the following results : · As our first main result, we prove that any homogeneous depth-3 Circuit for computing the product of d matrices of dimension n ×n requires Ω(nd−1/2d) size. This improves the lower bounds in [9] for d=ω(1). · As our second main result, we show that there is an explicit polynomial on n variables and degree at most $\frac{n}{2}$ for which any depth-3 Circuit C of product dimension at most $\frac{n}{10}$ (dimension of the space of affine forms feeding into each product gate) requires size 2Ω(n). This generalizes the lower bounds against diagonal Circuits proved in [14]. Diagonal Circuits are of product dimension 1. · We prove a nΩ(logn) lower bound on the size of product-sparse formulas. By definition, any multilinear formula is a product-sparse formula. Thus, this result extends the known super-polynomial lower bounds on the size of multilinear formulas [11]. · We prove a 2Ω(n) lower bound on the size of partitioned Arithmetic branching programs. This result extends the known exponential lower bound on the size of ordered Arithmetic branching programs [7].
N. Tomabechi - One of the best experts on this subject based on the ideXlab platform.
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Counter-based residue Arithmetic Circuit for VLSI digital signal processing systems
1988. IEEE International Symposium on Circuits and Systems, 1Co-Authors: N. TomabechiAbstract:The counter-based residue Arithmetic Circuit, which is composed of ring counters and performs residue Arithmetic operations by pulse counting, is proposed for the efficient implementation of VLSI digital signal processing systems. A masterslice LSI on which counter-based residue Arithmetic Circuits are regularly arranged is also presented. It is demonstrated that the counter-based residue Arithmetic Circuit has a simple, regular, and well partitioned structure, and that a highly regular and parallel architecture based on both the residue number system and pipelining can be realized. >
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Counter-based residue Arithmetic Circuit for easily testable VLSI digital signal processing systems
Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1Co-Authors: N. TomabechiAbstract:A counter-based residue Arithmetic Circuit composed of ring counters which performs residue Arithmetic operations by pulse counting is proposed for easily testable VLSI digital signal processing systems. A master-slice LSI on which counter-based residue Arithmetic Circuits are regularly arranged is also presented. It is demonstrated that the counter-based residue Arithmetic Circuit has a self-testable structure, and a highly regular and easily testable system implementation can be realized using the Circuits. >
Naofumi Homma - One of the best experts on this subject based on the ideXlab platform.
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formal design of pipelined gf Arithmetic Circuits and its application to cryptographic processors
International Symposium on Multiple-Valued Logic, 2016Co-Authors: Rei Ueno, Naofumi Homma, Yukihiro Sugawara, Takafumi AokiAbstract:This study presents a formal approach to designing pipelined Arithmetic Circuits over Galois fields (GFs). The proposed method extends a graph-based Circuit description known as a Galois-field Arithmetic Circuit graph (GF-ACG) to Linear-time Temporal Logic (LTL) in order to represent the timing property of pipelined Circuits. We first present the extension of GF-ACG and its formal verification using computer algebra. We then demonstrate the efficiency of the proposed method through an experimental design of a lightweight cryptographic processor. In particular, we design a tamper-resistant datapath with threshold Implementation (TI) based on pipelining and multi-party computation. The proposed method can verify the processor within 1 h, whereas conventional methods would fail.
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formal design of galois field Arithmetic Circuits based on polynomial ring representation
International Symposium on Multiple-Valued Logic, 2015Co-Authors: Rei Ueno, Naofumi Homma, Yukihiro Sugawara, Takafumi AokiAbstract:This paper presents a graph-based approach to designing Arithmetic Circuits over Galois fields (GFs) based on a polynomial ring (PR) representation, which is a redundant representation for GF Arithmetic. The proposed method extends a graph-based Circuit description, called a Galois-field Arithmetic Circuit graph (GF-ACG), which was originally proposed for no redundant GF Arithmetic. First, the extension of a GF-ACG is applied to the design and verification of the PR-based GFArithmetic Circuits. Then the efficiency of the proposed method is demonstrated using the design and verification of PR-based GF multipliers. In addition, GF(28) inversion Circuits with differentGF representations are designed and evaluated in order to confirm the significance of the PR representation.
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formal design of multiple valued Arithmetic algorithms over galois fields and its application to cryptographic processor
International Symposium on Multiple-Valued Logic, 2012Co-Authors: Naofumi Homma, Kazuya Saito, Takafumi AokiAbstract:This paper presents a formal description of multiple-valued Arithmetic algorithms over Galois Fields (GFs). Our graph-based method can be applied to any multiple-valued Arithmetic Circuit over GF(2^m). The proposed Circuit description is formally verified by formula manipulation based on polynomial reduction using Groebner basis. In this paper, we first present the graph representation and its extension. We also present an application of the proposed method to cryptographic processor consisting of GF(2^m) Arithmetic Circuits. The target architecture considered here is a round-per-cycle loop architecture commonly used in the design of cryptographic processors. The proposed approach successfully describes the 128-bit data path and verifies it within 4 minutes.
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ISMVL - Formal Design of Multiple-Valued Arithmetic Algorithms over Galois Fields and Its Application to Cryptographic Processor
2012 IEEE 42nd International Symposium on Multiple-Valued Logic, 2012Co-Authors: Naofumi Homma, Kazuya Saito, Takafumi AokiAbstract:This paper presents a formal description of multiple-valued Arithmetic algorithms over Galois Fields (GFs). Our graph-based method can be applied to any multiple-valued Arithmetic Circuit over GF(2^m). The proposed Circuit description is formally verified by formula manipulation based on polynomial reduction using Groebner basis. In this paper, we first present the graph representation and its extension. We also present an application of the proposed method to cryptographic processor consisting of GF(2^m) Arithmetic Circuits. The target architecture considered here is a round-per-cycle loop architecture commonly used in the design of cryptographic processors. The proposed approach successfully describes the 128-bit data path and verifies it within 4 minutes.
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Arithmetic Circuit Verification Based on Symbolic Computer Algebra
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2008Co-Authors: Yuki Watanabe, Takafumi Aoki, Naofumi Homma, Tatsuo HiguchiAbstract:This paper presents a formal approach to verify Arithmetic Circuits using symbolic computer algebra. Our method describes Arithmetic Circuits directly with high-level mathematical objects based on weighted number systems and Arithmetic formulae. Such Circuit description can be effectively verified by polynomial reduction techniques using Grobner Bases. In this paper, we describe how the symbolic computer algebra can be used to describe and verify Arithmetic Circuits. The advantageous effects of the proposed approach are demonstrated through experimental verification of some Arithmetic Circuits such as multiply-accumulator and FIR filter. The result shows that the proposed approach has a definite possibility of verifying practical Arithmetic Circuits.