The Experts below are selected from a list of 2700 Experts worldwide ranked by ideXlab platform

T S Hahn - One of the best experts on this subject based on the ideXlab platform.

  • A rapid single flux quantum 1 bit arithmetic logic unit constructed with a half-adder cell
    Superconductor Science and Technology, 2004
    Co-Authors: K R Jung, Alex F. Kirichenko, J Y Kim, Joonhee Kang, J H Park, T S Hahn
    Abstract:

    We have designed, fabricated, and tested a rapid single flux quantum (RSFQ) 1 bit arithmetic logic unit (ALU) block. The circuit consists of three DC current driven SFQ switches and a half-adder. We successfully tested the half-adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half-adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached two switches at the input ports of the half-adder to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this set-up, the circuit was successfully tested up to 20 GHz. The chip was fabricated using a standard HYPRES 1 kA cm−2 Nb Josephson junction fabrication process.

K R Jung - One of the best experts on this subject based on the ideXlab platform.

  • A rapid single flux quantum 1 bit arithmetic logic unit constructed with a half-adder cell
    Superconductor Science and Technology, 2004
    Co-Authors: K R Jung, Alex F. Kirichenko, J Y Kim, Joonhee Kang, J H Park, T S Hahn
    Abstract:

    We have designed, fabricated, and tested a rapid single flux quantum (RSFQ) 1 bit arithmetic logic unit (ALU) block. The circuit consists of three DC current driven SFQ switches and a half-adder. We successfully tested the half-adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half-adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached two switches at the input ports of the half-adder to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this set-up, the circuit was successfully tested up to 20 GHz. The chip was fabricated using a standard HYPRES 1 kA cm−2 Nb Josephson junction fabrication process.

Guang-ming Tang - One of the best experts on this subject based on the ideXlab platform.

  • logic design of a 16 bit bit slice arithmetic logic unit for 32 64 bit rsfq microprocessors
    IEEE Transactions on Applied Superconductivity, 2018
    Co-Authors: Guang-ming Tang, Dongrui Fan
    Abstract:

    A 16-bit bit-slice arithmetic logic unit (ALU) is proposed for 32-/64-bit rapid single-flux-quantum microprocessors. It is based on a Ladner-Fischer adder. The ALU covers all of the ALU operations for MIPS32 instructions set. And each of the two 64-bit operands is divided into four slices of 16 bits each. The ALU uses synchronous concurrent-flow clocking and consists of 11 pipeline stages. The proposed ALU can be used for any 16n-bit processing.

  • logic Design of a 16-bit Bit-Slice arithmetic logic unit for 32-/64-bit RSFQ Microprocessors
    IEEE Transactions on Applied Superconductivity, 2018
    Co-Authors: Guang-ming Tang, Dongrui Fan
    Abstract:

    A 16-bit bit-slice arithmetic logic unit (ALU) is proposed for 32-/64-bit rapid single-flux-quantum microprocessors. It is based on a Ladner-Fischer adder. The ALU covers all of the ALU operations for MIPS32 instructions set. And each of the two 64-bit operands is divided into four slices of 16 bits each. The ALU uses synchronous concurrent-flow clocking and consists of 11 pipeline stages. The proposed ALU can be used for any 16n-bit processing.

  • 4-bit Bit-Slice arithmetic logic unit for 32-bit RSFQ Microprocessors
    IEEE Transactions on Applied Superconductivity, 2016
    Co-Authors: Guang-ming Tang, Masamitsu Tanaka, Kazuyoshi Takagi, Kensuke Takata, Akira Fujimaki, Naofumi Takagi
    Abstract:

    A 4-bit bit-slice arithmetic logic unit (ALU) for 32-bit rapid single-flux-quantum microprocessors was demonstrated. The proposed ALU covers all of the ALU operations for the MIPS32 instruction set. It processes bit-sliced 32-bit data that are divided into eight slices of 4 bits. The bit-slice approach simplifies the circuit structure and reduces the hardware cost. The ALU uses synchronous concurrent-flow clocking and consists of eight pipeline stages. It was implemented using the 1.0- $\mu\mbox{m}\ \mbox{Nb}/\mbox{AlO}_{x}/\mbox{Nb}$ nine-layer advanced process 2 (ADP2) with a critical current density of 10 kA/cm2, and fabricated by National Institute of Advanced Industrial Science and Technology (AIST). It consists of 3481 Josephson junctions with an area of $3.09 \times 1.66\ \mbox{mm}^2$ . It achieved the target frequency of 50 GHz and a latency of 524 ps for a 32-bit operation, at the designed DC bias voltage of 2.5 mV, via precise control of interconnect delays and clock distribution. Furthermore, it achieved a throughput of $6.25 \times 10^9$ 32-bit operations per second. All the correct ALU operations with measured DC bias voltage margins of around 10% at 50 GHz were successfully obtained. The proposed ALU can be used for any $4n$ -bit processing.

Dongrui Fan - One of the best experts on this subject based on the ideXlab platform.

Naofumi Takagi - One of the best experts on this subject based on the ideXlab platform.

  • 4-bit Bit-Slice arithmetic logic unit for 32-bit RSFQ Microprocessors
    IEEE Transactions on Applied Superconductivity, 2016
    Co-Authors: Guang-ming Tang, Masamitsu Tanaka, Kazuyoshi Takagi, Kensuke Takata, Akira Fujimaki, Naofumi Takagi
    Abstract:

    A 4-bit bit-slice arithmetic logic unit (ALU) for 32-bit rapid single-flux-quantum microprocessors was demonstrated. The proposed ALU covers all of the ALU operations for the MIPS32 instruction set. It processes bit-sliced 32-bit data that are divided into eight slices of 4 bits. The bit-slice approach simplifies the circuit structure and reduces the hardware cost. The ALU uses synchronous concurrent-flow clocking and consists of eight pipeline stages. It was implemented using the 1.0- $\mu\mbox{m}\ \mbox{Nb}/\mbox{AlO}_{x}/\mbox{Nb}$ nine-layer advanced process 2 (ADP2) with a critical current density of 10 kA/cm2, and fabricated by National Institute of Advanced Industrial Science and Technology (AIST). It consists of 3481 Josephson junctions with an area of $3.09 \times 1.66\ \mbox{mm}^2$ . It achieved the target frequency of 50 GHz and a latency of 524 ps for a 32-bit operation, at the designed DC bias voltage of 2.5 mV, via precise control of interconnect delays and clock distribution. Furthermore, it achieved a throughput of $6.25 \times 10^9$ 32-bit operations per second. All the correct ALU operations with measured DC bias voltage margins of around 10% at 50 GHz were successfully obtained. The proposed ALU can be used for any $4n$ -bit processing.

  • 80-GHz Operation of an 8-Bit RSFQ arithmetic logic unit
    2015 15th International Superconductive Electronics Conference (ISEC), 2015
    Co-Authors: Yuki Ando, Ryo Sato, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi
    Abstract:

    We have designed and demonstrated an arithmetic logic unit (ALU) based on rapid single-flux-quantum (RSFQ) technology. The ALU has been developed toward demonstration of high-performance information processing using a general purpose microprocessor CORE e4. The target operation frequency of the ALU is 50 GHz. In this paper, we present the design and high- speed functionality test results of the ALU. The ALU can execute 10 instructions. We aimed at high frequency operation with precise timing design using logic gates synchronized to the clock signal. The ALU contains 1555 Josephson junctions (JJs) and occupies a circuit area of 0.53mm². We have demonstrated the correct operation of the ALU using on-chip high-speed test. The estimated maximum operating frequency based on measurement results is 80 GHz.