The Experts below are selected from a list of 195 Experts worldwide ranked by ideXlab platform
Tanay Karnik - One of the best experts on this subject based on the ideXlab platform.
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Resilient Microprocessor design for high performance & energy efficiency
2010 ACM IEEE International Symposium on Low-Power Electronics and Design (ISLPED), 2010Co-Authors: Keith A. Bowman, James W. Tschanz, Shih-lien L. Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris B. Wilkerson, Arijit Raychowdhury, Tanay KarnikAbstract:Conventional Microprocessors require a clock frequency (FCLK) guardband to ensure correct functionality during infrequent dynamic operating variations in supply voltage (VCC), temperature, and transistor aging. Consequently, these inflexible designs cannot exploit opportunities for higher performance by increasing FCLK or lower energy by reducing VCC during favorable operating conditions. This presentation describes a 45nm resilient Microprocessor with error-detection and recovery circuits to detect and correct timing errors from dynamic variations to mitigate the FCLK guardband, thus enabling higher performance or lower energy as compared to a conventional design. The Microprocessor core supports two distinct error-detection designs and two separate error-recovery techniques, allowing a direct comparison of the relative trade-offs. Silicon measurements demonstrate that resilient circuits enable a 41% throughput gain at equal energy or a 22% energy reduction at equal throughput, as compared to a conventional design when executing a benchmark program with a 10% VCC droop. In addition, the resilient circuits guide an adaptive clock controller that tracks recovery cycles and adapts to persistent variations by changing FCLK. The combination of error-detection and recovery circuits with dynamic adaptation allows the Microprocessor to adapt to the operating environment to deliver maximum efficiency. The presentation concludes by discussing the opportunity of applying resilient techniques to enhance the dynamic operating range (i.e., high-performance and low-power modes) for Microprocessors.
Steve Yurash - One of the best experts on this subject based on the ideXlab platform.
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ITC - Lessons from at-speed scan deployment on an Intel® Itanium® Microprocessor
2010 IEEE International Test Conference, 2010Co-Authors: Pankaj Pant, Joshua Zelman, Glenn Colon-bonet, Jennifer Flint, Steve YurashAbstract:Lessons learnt during the deployment of transition scan content on an Intel® Itanium® server Microprocessor design and its use for electrical debug and defect screening in high-volume manufacturing are described. While many publications in the area of transition scan show it being practiced as an efficient defect screening tool, only a minority of these designs were high-performance Microprocessor designs. This work illustrates the benefits of such techniques on complex Microprocessors.
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Lessons from at-speed scan deployment on an Intel® Itanium® Microprocessor
2010 IEEE International Test Conference, 2010Co-Authors: Pankaj Pant, Joshua Zelman, Glenn Colon-bonet, Jennifer Flint, Steve YurashAbstract:Lessons learnt during the deployment of transition scan content on an Intel® Itanium® server Microprocessor design and its use for electrical debug and defect screening in high-volume manufacturing are described. While many publications in the area of transition scan show it being practiced as an efficient defect screening tool, only a minority of these designs were high-performance Microprocessor designs. This work illustrates the benefits of such techniques on complex Microprocessors.
N. Borkar - One of the best experts on this subject based on the ideXlab platform.
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Design challenges in sub-100 nm high performance Microprocessors
17th International Conference on VLSI Design. Proceedings., 2004Co-Authors: S.g. Narendra, J. Tschanz, V. Erraguntla, N. BorkarAbstract:This article deals with design challenges for high performance Microprocessors. Device challenges including gate leakage, junction tunneling, junction depth scaling, parasitic series resistance, and short channel effects. Microprocessor frequencies are increasing every generation from additional architectural and circuit complexity, which demands higher level of integration and die size increase. To address these scaling challenges, devices, circuits and design methodologies need to evolve. Scaling gate oxide thickness is important for controlling short channel effects.
J. Tschanz - One of the best experts on this subject based on the ideXlab platform.
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Adaptive circuit techniques to minimize variation impacts on Microprocessor performance and power
2005 IEEE International Symposium on Circuits and Systems, 2005Co-Authors: J. Tschanz, S. Narendra, A. Keshavarzi, V. DeAbstract:Adaptive supply voltage and adaptive body bias may be used to control the frequency and leakage distribution of fabricated Microprocessor dies. Testchip measurements show that adaptive VCC is effective in reducing the impact of parameter variations on frequency, active power, and leakage power of Microprocessors when 20 mV VCC resolution is used. Using adaptive VCC together with adaptive VBS or WID-VBS is much more effective than using any of them individually.
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Design challenges in sub-100 nm high performance Microprocessors
17th International Conference on VLSI Design. Proceedings., 2004Co-Authors: S.g. Narendra, J. Tschanz, V. Erraguntla, N. BorkarAbstract:This article deals with design challenges for high performance Microprocessors. Device challenges including gate leakage, junction tunneling, junction depth scaling, parasitic series resistance, and short channel effects. Microprocessor frequencies are increasing every generation from additional architectural and circuit complexity, which demands higher level of integration and die size increase. To address these scaling challenges, devices, circuits and design methodologies need to evolve. Scaling gate oxide thickness is important for controlling short channel effects.
Ram S. Viswanath - One of the best experts on this subject based on the ideXlab platform.
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Critical aspects of high-performance Microprocessor packaging
MRS Bulletin, 2003Co-Authors: Venkata Prasad Atluri, Ravi V. Mahajan, Priyavadan R. Patel, Vijay S. Wakharkar, Gregory M. Chrysler, Debendra Mallik, Gaurang N. Choksi, John Tang, Chia-pin Chiu, Ram S. ViswanathAbstract:Historically, the primary function of Microprocessor packaging has been to facilitate electrical connectivity of the complex and intricate silicon Microprocessor chips to the printed circuit board while providing protection to the chips from the external environment. However, as Microprocessor performance continues to follow Moore's law, the package has evolved from a simple protective enclosure to a key enabler to performance. The art and science of semiconductor packaging has advanced radically over the past few decades as faster and more powerful Microprocessors with tens of millions of transistors continue to be available, which require more signal and power input/output connections as well as greater power-dissipation capabilities. Key drivers for the development of packaging technologies include power delivery, thermal management, and interconnect scaling, in which the space transformation from fine-featured silicon interconnects to the relatively coarse features seen on motherboards has to be enabled by the package. These drivers, under constant market-driven cost pressure, have led to increased demands on new materials and new package architectures to enable silicon performance. Significant advances have already been made in the areas of heat dissipation, power delivery, high-speed signaling, and high-density interconnects. It is expected that the future evolution of Microprocessors will be increasingly challenging in these areas. This article focuses on providing a broad perspective view of the evolution of Microprocessor packaging and discusses future challenges.
