The Experts below are selected from a list of 6147 Experts worldwide ranked by ideXlab platform

Yueqiang Cheng - One of the best experts on this subject based on the ideXlab platform.

  • secure and efficient software based attestation for industrial control devices with ARM Processors
    Annual Computer Security Applications Conference, 2017
    Co-Authors: Binbin Chen, Xinshu Dong, Guangdong Bai, Sumeet Jauhar, Yueqiang Cheng
    Abstract:

    For industrial control systems, ensuring the software integrity of their devices is a key security requirement. A pure software-based attestation solution is highly desirable for protecting legacy field devices that lack hardware root of trust (e.g., Trusted Platform Module). However, for the large population of field devices with ARM Processors, existing software-based attestation schemes either incur long attestation time or are insecure. In this paper, we design a novel memory stride technique that significantly reduces the attestation time while remaining secure against known attacks and their advanced variants on ARM platform. We analyze the scheme's security and performance based on the formal framework proposed by ARMknecht et al. [7] (with a necessary change to ensure its applicability in practical settings). We also implement memory stride on two models of real-world power grid devices that are widely deployed today, and demonstrate its superior performance.

  • ACSAC - Secure and Efficient Software-based Attestation for Industrial Control Devices with ARM Processors
    Proceedings of the 33rd Annual Computer Security Applications Conference, 2017
    Co-Authors: Binbin Chen, Xinshu Dong, Guangdong Bai, Sumeet Jauhar, Yueqiang Cheng
    Abstract:

    For industrial control systems, ensuring the software integrity of their devices is a key security requirement. A pure software-based attestation solution is highly desirable for protecting legacy field devices that lack hardware root of trust (e.g., Trusted Platform Module). However, for the large population of field devices with ARM Processors, existing software-based attestation schemes either incur long attestation time or are insecure. In this paper, we design a novel memory stride technique that significantly reduces the attestation time while remaining secure against known attacks and their advanced variants on ARM platform. We analyze the scheme's security and performance based on the formal framework proposed by ARMknecht et al. [7] (with a necessary change to ensure its applicability in practical settings). We also implement memory stride on two models of real-world power grid devices that are widely deployed today, and demonstrate its superior performance.

Patrick Longa - One of the best experts on this subject based on the ideXlab platform.

  • Four\(\mathbb {Q}\)NEON: Faster Elliptic Curve Scalar Multiplications on ARM Processors
    Lecture Notes in Computer Science, 2017
    Co-Authors: Patrick Longa
    Abstract:

    We present a high-speed, high-security implementation of the recently proposed elliptic curve Four\(\mathbb {Q}\) (ASIACRYPT 2015) for 32-bit ARM Processors with NEON support. Exploiting the versatile and compact arithmetic of this curve, we design a vectorized implementation that achieves high-performance across a large variety of ARM platforms. Our software is fully protected against timing and cache attacks, and showcases the impressive speed of Four\(\mathbb {Q}\) when compared with other curve-based alternatives. For example, one single variable-base scalar multiplication is computed in about 235,000 Cortex-A8 cycles or 132,000 Cortex-A15 cycles which, compared to the results of the fastest genus 2 Kummer and Curve25519 implementations on the same platforms, offer speedups between 1.3x–1.7x and between 2.1x–2.4x, respectively. In comparison with the NIST standard curve K-283, we achieve speedups above 4x and 5.5x.

  • four mathbb q neon faster elliptic curve scalar multiplications on ARM Processors
    International Conference on Selected areas in Cryptography, 2016
    Co-Authors: Patrick Longa
    Abstract:

    We present a high-speed, high-security implementation of the recently proposed elliptic curve Four\(\mathbb {Q}\) (ASIACRYPT 2015) for 32-bit ARM Processors with NEON support. Exploiting the versatile and compact arithmetic of this curve, we design a vectorized implementation that achieves high-performance across a large variety of ARM platforms. Our software is fully protected against timing and cache attacks, and showcases the impressive speed of Four\(\mathbb {Q}\) when compared with other curve-based alternatives. For example, one single variable-base scalar multiplication is computed in about 235,000 Cortex-A8 cycles or 132,000 Cortex-A15 cycles which, compared to the results of the fastest genus 2 Kummer and Curve25519 implementations on the same platforms, offer speedups between 1.3x–1.7x and between 2.1x–2.4x, respectively. In comparison with the NIST standard curve K-283, we achieve speedups above 4x and 5.5x.

  • fourqneon faster elliptic curve scalar multiplications on ARM Processors
    SAC, 2016
    Co-Authors: Patrick Longa
    Abstract:

    We present a high-speed, high-security implementation of the recently proposed elliptic curve FourQ (ASIACRYPT 2015) for 32-bit ARM Processors with NEON support. Exploiting the versatile and compact arithmetic of this curve, we design a vectorized implementation that achieves high-performance across a large variety of ARM platforms. Our software is fully protected against timing and cache attacks, and showcases the impressive speed of FourQ when compared with other curve-based alternatives. For example, one single variable-base scalar multiplication is computed in about 235,000 Cortex-A8 cycles or 132,000 Cortex-A15 cycles which, compared to the results of the fastest genus 2 Kummer and Curve25519 implementations on the same platforms, offer speedups between 1.3x-1.7x and between 2.1x-2.4x, respectively. In comparison with the NIST standard curve K-283, we achieve speedups above 4x and 5.5x.

  • Efficient and secure algorithms for GLV-based scalar multiplication and their implementation on GLV–GLS curves (extended version)
    Journal of Cryptographic Engineering, 2015
    Co-Authors: Armando Faz-hernández, Patrick Longa, Ana H. Sánchez
    Abstract:

    We propose efficient algorithms and formulas that improve the performance of side channel protected elliptic curve computations with special focus on scalar multiplication exploiting the Gallant–Lambert–Vanstone (CRYPTO 2001 ) and Galbraith–Lin–Scott (EUROCRYPT 2009 ) methods. Firstly, by adapting Feng et al.’s recoding to the GLV setting, we derive new regular algorithms for variable-base scalar multiplication that offer protection against simple side-channel and timing attacks. Secondly, we propose an efficient, side-channel protected algorithm for fixed-base scalar multiplication which combines Feng et al.’s recoding with Lim-Lee’s comb method. Thirdly, we propose an efficient technique that interleaves ARM and NEON-based multiprecision operations over an extension field to improve performance of GLS curves on modern ARM Processors. Finally, we showcase the efficiency of the proposed techniques by implementing a state-of-the-art GLV–GLS curve in twisted Edwards form defined over $$\mathbb {F}_{p^2}$$ F p 2 , which supports a four-dimensional decomposition of the scalar and is fully protected against timing attacks. Analysis and performance results are reported for modern $$\times $$ × 64 and ARM Processors. For instance, we compute a variable-base scalar multiplication in 89,000 and 244,000 cycles on an Intel Ivy Bridge and an ARM Cortex-A15 processor (respect.); using a precomputed table of 6KB, we compute a fixed-base scalar multiplication in 49,000 and 116,000 cycles (respect.); and using a precomputed table of 3KB, we compute a double-scalar multiplication in 115,000 and 285,000 cycles (respect.). The proposed techniques represent an important improvement of the state-of-the-art performance of elliptic curve computations, and allow us to set new speed records in several modern Processors. The techniques also reduce the cost of adding protection against timing attacks in the computation of GLV-based variable-base scalar multiplication to below 10 %. This work is the extended version of a publication that appeared at CT-RSA (Faz-Hernández et al. Topics in Cryptology, CT-RSA 2014, vol. 8366, pp. 1–27 2014 ).

  • Selected Areas in Cryptography - Efficient Implementation of Bilinear Pairings on ARM Processors
    Selected Areas in Cryptography, 2013
    Co-Authors: Gurleen Grewal, Patrick Longa, Reza Azarderakhsh, David Jao
    Abstract:

    As hardware capabilities increase, low-power devices such as smartphones represent a natural environment for the efficient implementation of cryptographic pairings. Few works in the literature have considered such platforms despite their growing importance in a post-PC world. In this paper, we investigate the efficient computation of the Optimal-Ate pairing over Barreto-Naehrig curves in software at different security levels on ARM Processors. We exploit state-of-the-art techniques and propose new optimizations to speed up the computation in the tower field and curve arithmetic. In particular, we extend the concept of lazy reduction to inversion in extension fields, analyze an efficient alternative for the sparse multiplication used inside the Miller’s algorithm and reduce further the cost of point/line evaluation formulas in affine and projective homogeneous coordinates. In addition, we study the efficiency of using M-type sextic twists in the pairing computation and carry out a detailed comparison between affine and projective coordinate systems. Our implementations on various mass-market smartphones and tablets significantly improve the state-of-the-art of pairing computation on ARM-powered devices, outperforming by at least a factor of 3.7 the best previous results in the literature.

Binbin Chen - One of the best experts on this subject based on the ideXlab platform.

  • secure and efficient software based attestation for industrial control devices with ARM Processors
    Annual Computer Security Applications Conference, 2017
    Co-Authors: Binbin Chen, Xinshu Dong, Guangdong Bai, Sumeet Jauhar, Yueqiang Cheng
    Abstract:

    For industrial control systems, ensuring the software integrity of their devices is a key security requirement. A pure software-based attestation solution is highly desirable for protecting legacy field devices that lack hardware root of trust (e.g., Trusted Platform Module). However, for the large population of field devices with ARM Processors, existing software-based attestation schemes either incur long attestation time or are insecure. In this paper, we design a novel memory stride technique that significantly reduces the attestation time while remaining secure against known attacks and their advanced variants on ARM platform. We analyze the scheme's security and performance based on the formal framework proposed by ARMknecht et al. [7] (with a necessary change to ensure its applicability in practical settings). We also implement memory stride on two models of real-world power grid devices that are widely deployed today, and demonstrate its superior performance.

  • ACSAC - Secure and Efficient Software-based Attestation for Industrial Control Devices with ARM Processors
    Proceedings of the 33rd Annual Computer Security Applications Conference, 2017
    Co-Authors: Binbin Chen, Xinshu Dong, Guangdong Bai, Sumeet Jauhar, Yueqiang Cheng
    Abstract:

    For industrial control systems, ensuring the software integrity of their devices is a key security requirement. A pure software-based attestation solution is highly desirable for protecting legacy field devices that lack hardware root of trust (e.g., Trusted Platform Module). However, for the large population of field devices with ARM Processors, existing software-based attestation schemes either incur long attestation time or are insecure. In this paper, we design a novel memory stride technique that significantly reduces the attestation time while remaining secure against known attacks and their advanced variants on ARM platform. We analyze the scheme's security and performance based on the formal framework proposed by ARMknecht et al. [7] (with a necessary change to ensure its applicability in practical settings). We also implement memory stride on two models of real-world power grid devices that are widely deployed today, and demonstrate its superior performance.

Nadia Tawbi - One of the best experts on this subject based on the ideXlab platform.

  • ARMed e bunny a selective dynamic compiler for embedded java virtual machine targeting ARM Processors
    ACM Symposium on Applied Computing, 2005
    Co-Authors: Mourad Debbabi, Azzam Mourad, Nadia Tawbi
    Abstract:

    This paper presents a new selective dynamic compilation technique targeting ARM 16/32-bit embedded system Processors. This compiler is built inside the J2ME/CLDC (Java 2 Micro Edition for Connected Limited Device Configuration) platform [8]. The primary objective of our work is to come up with an efficient, lightweight and low-footprint accelerated Java virtual machine ready to be executed on embedded machines. This is achieved by implementing a selective ARM dynamic compiler called ARMed E-Bunny into Sun's Kilobyte Virtual Machine (KVM) [9]. In this paper, we present the motivations, the requirements, the architecture, the design, the implementation and debugging issues of ARMed E-Bunny. The modified KVM is ported on an Embedded-Linux PDA and is tested using standard J2ME benchmarks. The experimental results on its performance demonstrate that a speedup of 360% over the last version of Sun's KVM is accomplished with a footprint overhead that does not exceed 119KB.

Ning Zhang - One of the best experts on this subject based on the ideXlab platform.

  • satin a secure and trustworthy asynchronous introspection on multi core ARM Processors
    Dependable Systems and Networks, 2019
    Co-Authors: Shengye Wan, Kun Sun, Jianhua Sun, Ning Zhang
    Abstract:

    On ARM Processors with TrustZone security extension, asynchronous introspection mechanisms have been developed in the secure world to detect security policy violations in the normal world. These mechanisms provide security protection via passively checking the normal world snapshot. However, since previous secure world checking solutions require to suspend the entire rich OS, asynchronous introspection has not been widely adopted in the real world. Given a multi-core ARM system that can execute the two worlds simultaneously on different cores, secure world introspection can check the rich OS without suspension. However, we identify a new normal-world evasion attack that can defeat the asynchronous introspection by removing the attacking traces in parallel from one core when the security checking is performing on another core. We perform a systematic study on this attack and present its efficiency against existing asynchronous introspection mechanisms. As the countermeasure, we propose a secure and trustworthy asynchronous introspection mechanism called SATIN, which can efficiently detect the evasion attacks by increasing the attackers' evasion time cost and decreasing the defender's execution time under a safe limit. We implement a prototype on an ARM development board and the experimental results show that SATIN can effectively prevent evasion attacks on multi-core systems with a minor system overhead.

  • DSN - SATIN: A Secure and Trustworthy Asynchronous Introspection on Multi-Core ARM Processors
    2019 49th Annual IEEE IFIP International Conference on Dependable Systems and Networks (DSN), 2019
    Co-Authors: Shengye Wan, Kun Sun, Jianhua Sun, Ning Zhang
    Abstract:

    On ARM Processors with TrustZone security extension, asynchronous introspection mechanisms have been developed in the secure world to detect security policy violations in the normal world. These mechanisms provide security protection via passively checking the normal world snapshot. However, since previous secure world checking solutions require to suspend the entire rich OS, asynchronous introspection has not been widely adopted in the real world. Given a multi-core ARM system that can execute the two worlds simultaneously on different cores, secure world introspection can check the rich OS without suspension. However, we identify a new normal-world evasion attack that can defeat the asynchronous introspection by removing the attacking traces in parallel from one core when the security checking is performing on another core. We perform a systematic study on this attack and present its efficiency against existing asynchronous introspection mechanisms. As the countermeasure, we propose a secure and trustworthy asynchronous introspection mechanism called SATIN, which can efficiently detect the evasion attacks by increasing the attackers' evasion time cost and decreasing the defender's execution time under a safe limit. We implement a prototype on an ARM development board and the experimental results show that SATIN can effectively prevent evasion attacks on multi-core systems with a minor system overhead.

  • case cache assisted secure execution on ARM Processors
    IEEE Symposium on Security and Privacy, 2016
    Co-Authors: Ning Zhang, Kun Sun, Wenjing Lou, Thomas Y Hou
    Abstract:

    Recognizing the pressing demands to secure embedded applications, ARM TrustZone has been adopted in both academic research and commercial products to protect sensitive code and data in a privileged, isolated execution environment. However, the design of TrustZone cannot prevent physical memory disclosure attacks such as cold boot attack from gaining unrestricted read access to the sensitive contents in the dynamic random access memory (DRAM). A number of system-on-chip (SoC) bound execution solutions have been proposed to thaw the cold boot attack by storing sensitive data only in CPU registers, CPU cache or internal RAM. However, when the operating system, which is responsible for creating and maintaining the SoC-bound execution environment, is compromised, all the sensitive data is leaked. In this paper, we present the design and development of a cache-assisted secure execution framework, called CaSE, on ARM Processors to defend against sophisticated attackers who can launch multi-vector attacks including software attacks and hardware memory disclosure attacks. CaSE utilizes TrustZone and Cache-as-RAM technique to create a cache-based isolated execution environment, which can protect both code and data of security-sensitive applications against the compromised OS and the cold boot attack. To protect the sensitive code and data against cold boot attack, applications are encrypted in memory and decrypted only within the processor for execution. The memory separation and the cache separation provided by TrustZone are used to protect the cached applications against compromised OS. We implement a prototype of CaSE on the i.MX53 running ARM Cortex-A8 processor. The experimental results show that CaSE incurs small impacts on system performance when executing cryptographic algorithms including AES, RSA, and SHA1.