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Rajesh Gupta – One of the best experts on this subject based on the ideXlab platform.

  • ABSTRACT Partial Order Reduction for Scalable Testing of SystemC TLM Designs
    , 2013
    Co-Authors: Sudipta Kundu, Malay Ganai, Rajesh Gupta

    Abstract:

    A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is nondeterministic. To leverage testing of a SystemC TLM design, we focus on automatically exploring all possible behaviors of the design for a given data input. We combine static and dynamic partial order reduction techniques with SystemC semantics to intelligently explore a subset of the possible traces, while still being provably sufficient for detecting deadlocks and safety property Violations. We have implemented our exploration algorithm in a framework called Satya and have applied it to a variety of examples including the TAC benchmark. Using Satya, we automatically found an Assertion Violation in a benchmark distributed as a part of the OSCI repository

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  • DAC – Partial order reduction for scalable testing of systemC TLM designs
    Proceedings of the 45th annual conference on Design automation – DAC '08, 2008
    Co-Authors: Sudipta Kundu, Malay Ganai, Rajesh Gupta

    Abstract:

    A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is non- deterministic. To leverage testing of a SystemC TLM design, we focus on automatically exploring all possible behaviors of the design for a given data input. We combine static and dynamic partial order reduction techniques with SystemC semantics to intelligently explore a subset of the possible traces, while still being provably sufficient for detecting deadlocks and safety property Violations. We have implemented our exploration algorithm in a framework called Satya and have applied it to a variety of examples including the TAC benchmark. Using Satya, we automatically found an Assertion Violation in a benchmark distributed as a part of the OSCI repository.

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Ahmed Sobeih – One of the best experts on this subject based on the ideXlab platform.

  • Assertion Checking in J-Sim Simulation Models of Network Protocols
    SIMULATION, 2009
    Co-Authors: Ahmed Sobeih, Marcelo D'amorim, Mahesh Viswanathan, Darko Marinov

    Abstract:

    Verification and validation (V&V) is a critically important phase in the development life cycle of a simulation model. In the context of network simulation, traditional network simulators perform well in using a simulation model for evaluating the performance of a network protocol but lack the capability to check the “correctness” of the simulation model being used. To address this problem, we have extended J-Sim—an open-source component-based network simulator written entirely in Java—with a state space exploration (SSE) capability that explores the state space created by a network simulation model, up to a configurable maximum depth, in order to find an execution (if any) that violates an Assertion, i.e. a property specifying an invariant that must always hold true in all states. In this paper, we elaborate on the SSE framework in J-Sim and present one of our fairly complex case studies, namely verifying the simulation model of the Ad-hoc On-demand Distance Vector (AODV) routing protocol for wireless ad-hoc networks. The SSE framework makes use of protocol-specific properties along two orthogonal dimensions: state similarity and state ranking. State similarity determines whether a state is “similar to” another in order to enable the implementation of stateful search. State ranking determines whether a state is “better than” another in order to enable the implementation of best-first search (BeFS). Specifically, we develop protocol-specific search heuristics to guide SSE towards finding Assertion Violations in less time. We evaluate the efficiency of our SSE framework by comparing its performance with that of a state-of-the-art model checker for Java programs, namely Java PathFinder (JPF). The results of the comparison show that the time needed to find an Assertion Violation by our SSE framework in J-Sim can be significantly less than that in JPF unless a substantial amount of programming effort is spent in JPF to make its performance close to that of our SSE framework.

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  • Verification of simulation models of network protocols using state space exploration
    , 2008
    Co-Authors: Mahesh Viswanathan, Ahmed Sobeih

    Abstract:

    Verification and Validation (VV i.e., a property that must always hold true in all states.
    In this thesis, we present the design and implementation of the state space exploration framework in J-Sim. Furthermore, we demonstrate its usefulness and effectiveness in verifying complicated simulation models. Specifically, we verify the simulation models of two widely used and fairly complex routing and data dissemination protocols: the Ad-hoc On-Demand Distance Vector (AODV) routing protocol for wireless ad-hoc networks and the directed diffusion data dissemination protocol for wireless sensor networks. Moreover, we verify the simulation model of a reliable unicast protocol: the Automatic Repeat reQuest ( ARQ) protocol.
    To enable the verification of these fairly complex network simulation models, we make use of protocol-specific properties along two orthogonal dimensions: state similarity and state ranking. State similarity determines whether a state is “similar to” another in order to enable the implementation of stateful search. On the other hand, state ranking determines whether a state is “better than” another with respect to the implementation of best-first search (BeFS). Specifically, we develop protocol-specific search heuristics to guide state space exploration towards finding Assertion Violations in less time. In particular, we report findings on how to devise good search heuristics for routing/data dissemination protocols similar to AODV and directed diffusion.
    We evaluate the efficiency of our state space exploration framework by comparing its performance to that of a state-of-the-art model checker for Java programs, namely Java PathFinder (JPF). The results of the comparison show that the time needed to find an Assertion Violation by our state space exploration framework in J-Sim can be significantly less than that in JPF unless a significant amount of programming effort is done in JPF to make its performance close to that of our SSE framework.
    Finally, we present incremental state space exploration (ISSE), a technique that aims to provide a speedup in the state space exploration time of evolving simulation models; i.e., simulation models whose code changes from one version to another. A code change may or may not lead to a behavioral change. We analytically obtain necessary conditions for the ISSE technique to provide a speedup in the state space exploration time when compared to a traditional (non-incremental) SSE technique. We applied the ISSE technique to our case studies. In two case studies (namely AODV and directed diffusion), ISSE provided a speedup whereas in one case study (namely ARQ), it did not provide a speedup because the necessary conditions were violated.

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  • Verification of Simulation Models of Network Protocols Using State Space Exploration and Protocol-Specific Properties
    , 2007
    Co-Authors: Ahmed Sobeih, Marcelo D'amorim, Mahesh Viswanathan, Darko Marinov

    Abstract:

    Verification and Validation (VV i.e., a safety property. In this paper, we elaborate on the state space exploration framework in J-Sim and demonstrate its usefulness and effectiveness in verifying complicated simulation models. Specifically, we verify the simulation models of two widely used and fairly complex network protocols: the Ad-Hoc On-Demand Distance Vector (AODV) routing protocol for wireless ad hoc networks and the directed diffusion data dissemination protocol for wireless sensor networks. To enable the verification of these fairly complex network simulation models, we make use of structural properties in the underlying state space along two orthogonal dimensions; the first uses a non-trivial simulation relation to prune the states to be searched, and the second is state ranking that determines whether a state is “better than” another in order to enable the implementation of a best-first search (BeFS). We also develop protocol-specific search heuristics to guide state space exploration towards finding Assertion Violations in less time. In particular, we report findings on how to devise good search heuristics for routing/data dissemination protocols similar to AODV and directed diffusion. We also show that the time needed to find an Assertion Violation by our state space exploration framework in J-Sim is comparable to that of Java PathFinder (JPF), a state-of-the-art model checker for Java programs.1

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Maren Brockmeyer – One of the best experts on this subject based on the ideXlab platform.

  • A flexible, extensible simulation environment for testing real-time specifications
    IEEE Transactions on Computers, 2000
    Co-Authors: Maren Brockmeyer, C. Heitmeyer, F. Jahanlan, Ellen Winner

    Abstract:

    This paper describes MTSim, an extensible, customizable simulation platform for the Modechart toolset (MT). MTSim provides support for “plugging in” user-defined viewers useful in simulating system behavior in different ways, including application-specific ways. MTSim also supports full user participation in the generation of simulations by allowing users to inject events into the execution trace. Moreover, MTSim provides monitoring and Assertion checking of execution traces and the invocation of user-specified handlers upon Assertion Violation. This paper also introduces an MTSim component called WebSim, a suite of simulation tools for MT, and an application-specific component of MTSim which displays the cockpit of an F-18 aircraft and which responds to user inputs to model a bomb release function.

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  • HASE – A software environment for custom simulation and monitoring of real-time specifications
    Proceedings 1997 High-Assurance Engineering Workshop, 1997
    Co-Authors: Maren Brockmeyer, Farnam Jahanian, C. Heitmeyer, Ellen Winner, B. Labaw

    Abstract:

    The testing and validation of formal specifications of high assurance real time systems requires an extensible simulation environment with support for users to generate events, customize displays, and monitor event traces. The paper describes MTSim, a customizable simulation platform for the Modechart Toolset (MT). MTSim provides support for “plugging in” user defined viewers as well as user participation in the generation of simulations by allowing users to inject events into the execution trace. Moreover, MTSim provides monitoring and Assertion checking of execution traces and the invocation of user specified handlers upon Assertion Violation. The paper also introduces a MTSim component called WebSim, a suite of simulation tools for MT, and an application specific component of MTSim, which displays the cockpit of an F-18 aircraft and models its bomb release function.

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  • IEEE Real Time Technology and Applications Symposium – A flexible, extensible simulation environment for testing real-time specifications
    Proceedings Third IEEE Real-Time Technology and Applications Symposium, 1997
    Co-Authors: Maren Brockmeyer, Farnam Jahanian, C. Heitmeyer, B. Labaw

    Abstract:

    This paper describes MTSim, an extensible, customizable simulation platform for the Modechart toolset (MT). MTSim provides support for “plugging in” user-defined viewers useful an simulating system behavior in different ways, including application-specific ways. MTSim also supports full user participation in the generation of simulations by allowing users to inject events into the execution trace. Moreover, MTSim provides monitoring and Assertion checking of execution traces and the invocation of user-specified handlers upon Assertion Violation. This paper also introduces a MTSim component called WebSim, a suite of simulation tools for MT, and an an application-specific component of MTSim, which displays the cockpit of an F-18 aircraft and models its bomb release function.

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