The Experts below are selected from a list of 705 Experts worldwide ranked by ideXlab platform
Zhiniang Peng - One of the best experts on this subject based on the ideXlab platform.
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Efficient hardware implementation of PMI+ for low-resource devices in mobile cloud computing
Future Generation Computer Systems, 2015Co-Authors: Shaohua Tang, Guomin Chen, Zhiniang Peng, Adama Diene, Xiaofeng ChenAbstract:With rapid development of cloud computing, security issues have gained more and more attention, especially in mobile cloud computing environment. Smart phones and other mobile devices provide a lot of convenience to us, but due to its intrinsic low-resource limitation, it also causes many security problems. In this paper, we design a hardware that can efficiently implement PMI+, which is a Multivariate Quadratic (MQ) Asymmetric Cipher, for low-resource devices in mobile cloud computing. Our main contributions are that, firstly, hardware architectures of encryption and decryption of PMI+ are developed, and descriptions of corresponding hardware algorithm are proposed; secondly, basic arithmetic units are implemented with higher efficiency that multiplication, squaring, vector dot product and power operation are implemented in full parallel; and thirdly, optimized implementations for core modules, including optimized large power operation, are achieved. The encryption and decryption hardware of PMI+ is efficiently realized on FPGA by the above optimization and improvement. It is verified by experiments that the designed hardware can complete an encryption operation within 497 clock cycles, and the clock frequency can be up to 145.60 MHz, and the designed hardware can complete a decryption operation within 438 clock cycles wherein the clock frequency can be up to 132.21 MHz. Our experiment results also confirm that our design can be deployed in low-resource devices as thin client of mobile cloud computing. We design a hardware to implement MQ Asymmetric Cipher PMI+ for low-resource devices.Basic arithmetic units are implemented in optimized and full parallel.Our design can complete a large power operation in 16 clock cycles.Our hardware can complete an encryption operation of PMI+ within 497 clock cycles, and a decryption operation within 438 clock cycles.Our design has a good performance in cycle-area products.
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efficient hardware implementation of mq Asymmetric Cipher pmi on fpgas
Information Security Practice and Experience, 2014Co-Authors: Shaohua Tang, Guomin Chen, Zhiniang PengAbstract:PMI+ is a Multivariate Quadratic (MQ) public key algorithm used for encryption and decryption operations, and belongs to post quantum cryptography. We designs a hardware on FPGAs to efficiently implement PMI+ in this paper. Our main contributions are that, firstly, a hardware architecture of encryption and decryption of PMI+ is developed, and description of corresponding hardware algorithm is proposed; secondly, basic arithmetic units are implemented with higher efficiency that multiplication, squaring, vector dot product and power operation are implemented in full parallel; and thirdly, an optimized implementation for core module, including optimized large power operation, is achieved. The encryption and decryption hardware of PMI+ is efficiently realized on FPGA by the above optimization and improvement. It is verified by experiments that the designed hardware can complete an encryption operation within 497 clock cycles, and the clock frequency can be up to 145.6MHz, and the designed hardware can complete a decryption operation within 438 clock cycles wherein the clock frequency can be up to 37.04MHz.
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ISPEC - Efficient Hardware Implementation of MQ Asymmetric Cipher PMI+ on FPGAs
Information Security Practice and Experience, 2014Co-Authors: Shaohua Tang, Guomin Chen, Zhiniang PengAbstract:PMI+ is a Multivariate Quadratic (MQ) public key algorithm used for encryption and decryption operations, and belongs to post quantum cryptography. We designs a hardware on FPGAs to efficiently implement PMI+ in this paper. Our main contributions are that, firstly, a hardware architecture of encryption and decryption of PMI+ is developed, and description of corresponding hardware algorithm is proposed; secondly, basic arithmetic units are implemented with higher efficiency that multiplication, squaring, vector dot product and power operation are implemented in full parallel; and thirdly, an optimized implementation for core module, including optimized large power operation, is achieved. The encryption and decryption hardware of PMI+ is efficiently realized on FPGA by the above optimization and improvement. It is verified by experiments that the designed hardware can complete an encryption operation within 497 clock cycles, and the clock frequency can be up to 145.6MHz, and the designed hardware can complete a decryption operation within 438 clock cycles wherein the clock frequency can be up to 37.04MHz.
Shaohua Tang - One of the best experts on this subject based on the ideXlab platform.
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Efficient hardware implementation of PMI+ for low-resource devices in mobile cloud computing
Future Generation Computer Systems, 2015Co-Authors: Shaohua Tang, Guomin Chen, Zhiniang Peng, Adama Diene, Xiaofeng ChenAbstract:With rapid development of cloud computing, security issues have gained more and more attention, especially in mobile cloud computing environment. Smart phones and other mobile devices provide a lot of convenience to us, but due to its intrinsic low-resource limitation, it also causes many security problems. In this paper, we design a hardware that can efficiently implement PMI+, which is a Multivariate Quadratic (MQ) Asymmetric Cipher, for low-resource devices in mobile cloud computing. Our main contributions are that, firstly, hardware architectures of encryption and decryption of PMI+ are developed, and descriptions of corresponding hardware algorithm are proposed; secondly, basic arithmetic units are implemented with higher efficiency that multiplication, squaring, vector dot product and power operation are implemented in full parallel; and thirdly, optimized implementations for core modules, including optimized large power operation, are achieved. The encryption and decryption hardware of PMI+ is efficiently realized on FPGA by the above optimization and improvement. It is verified by experiments that the designed hardware can complete an encryption operation within 497 clock cycles, and the clock frequency can be up to 145.60 MHz, and the designed hardware can complete a decryption operation within 438 clock cycles wherein the clock frequency can be up to 132.21 MHz. Our experiment results also confirm that our design can be deployed in low-resource devices as thin client of mobile cloud computing. We design a hardware to implement MQ Asymmetric Cipher PMI+ for low-resource devices.Basic arithmetic units are implemented in optimized and full parallel.Our design can complete a large power operation in 16 clock cycles.Our hardware can complete an encryption operation of PMI+ within 497 clock cycles, and a decryption operation within 438 clock cycles.Our design has a good performance in cycle-area products.
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efficient hardware implementation of mq Asymmetric Cipher pmi on fpgas
Information Security Practice and Experience, 2014Co-Authors: Shaohua Tang, Guomin Chen, Zhiniang PengAbstract:PMI+ is a Multivariate Quadratic (MQ) public key algorithm used for encryption and decryption operations, and belongs to post quantum cryptography. We designs a hardware on FPGAs to efficiently implement PMI+ in this paper. Our main contributions are that, firstly, a hardware architecture of encryption and decryption of PMI+ is developed, and description of corresponding hardware algorithm is proposed; secondly, basic arithmetic units are implemented with higher efficiency that multiplication, squaring, vector dot product and power operation are implemented in full parallel; and thirdly, an optimized implementation for core module, including optimized large power operation, is achieved. The encryption and decryption hardware of PMI+ is efficiently realized on FPGA by the above optimization and improvement. It is verified by experiments that the designed hardware can complete an encryption operation within 497 clock cycles, and the clock frequency can be up to 145.6MHz, and the designed hardware can complete a decryption operation within 438 clock cycles wherein the clock frequency can be up to 37.04MHz.
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ISPEC - Efficient Hardware Implementation of MQ Asymmetric Cipher PMI+ on FPGAs
Information Security Practice and Experience, 2014Co-Authors: Shaohua Tang, Guomin Chen, Zhiniang PengAbstract:PMI+ is a Multivariate Quadratic (MQ) public key algorithm used for encryption and decryption operations, and belongs to post quantum cryptography. We designs a hardware on FPGAs to efficiently implement PMI+ in this paper. Our main contributions are that, firstly, a hardware architecture of encryption and decryption of PMI+ is developed, and description of corresponding hardware algorithm is proposed; secondly, basic arithmetic units are implemented with higher efficiency that multiplication, squaring, vector dot product and power operation are implemented in full parallel; and thirdly, an optimized implementation for core module, including optimized large power operation, is achieved. The encryption and decryption hardware of PMI+ is efficiently realized on FPGA by the above optimization and improvement. It is verified by experiments that the designed hardware can complete an encryption operation within 497 clock cycles, and the clock frequency can be up to 145.6MHz, and the designed hardware can complete a decryption operation within 438 clock cycles wherein the clock frequency can be up to 37.04MHz.
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CIS (2) - A CPK-Based Security Scheme at Network Layer
2009 International Conference on Computational Intelligence and Security, 2009Co-Authors: Zhiyuan Xie, Shaohua TangAbstract:A novel security scheme at network layer is proposed. It provides mutual authentication between the communication partners by adopting the effective combined public key (CPK) algorithm, which is an identity-based cryptosystem. And each outgoing packet can be digitally signed with CPK-based signature, which uses elliptic curve digital signature algorithm (ECDSA) and may offer equal security with a far smaller key size than RSA’ s, to provide packet-level nonrepudiation when necessary. In addition, the data transmitted over the network can be encrypted for better security via a symmetric or Asymmetric Cipher. Compared to similar network security solutions, the proposed scheme is easier to configure and more flexible. The experimental results show that the scheme owns better efficiency.
Guomin Chen - One of the best experts on this subject based on the ideXlab platform.
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Efficient hardware implementation of PMI+ for low-resource devices in mobile cloud computing
Future Generation Computer Systems, 2015Co-Authors: Shaohua Tang, Guomin Chen, Zhiniang Peng, Adama Diene, Xiaofeng ChenAbstract:With rapid development of cloud computing, security issues have gained more and more attention, especially in mobile cloud computing environment. Smart phones and other mobile devices provide a lot of convenience to us, but due to its intrinsic low-resource limitation, it also causes many security problems. In this paper, we design a hardware that can efficiently implement PMI+, which is a Multivariate Quadratic (MQ) Asymmetric Cipher, for low-resource devices in mobile cloud computing. Our main contributions are that, firstly, hardware architectures of encryption and decryption of PMI+ are developed, and descriptions of corresponding hardware algorithm are proposed; secondly, basic arithmetic units are implemented with higher efficiency that multiplication, squaring, vector dot product and power operation are implemented in full parallel; and thirdly, optimized implementations for core modules, including optimized large power operation, are achieved. The encryption and decryption hardware of PMI+ is efficiently realized on FPGA by the above optimization and improvement. It is verified by experiments that the designed hardware can complete an encryption operation within 497 clock cycles, and the clock frequency can be up to 145.60 MHz, and the designed hardware can complete a decryption operation within 438 clock cycles wherein the clock frequency can be up to 132.21 MHz. Our experiment results also confirm that our design can be deployed in low-resource devices as thin client of mobile cloud computing. We design a hardware to implement MQ Asymmetric Cipher PMI+ for low-resource devices.Basic arithmetic units are implemented in optimized and full parallel.Our design can complete a large power operation in 16 clock cycles.Our hardware can complete an encryption operation of PMI+ within 497 clock cycles, and a decryption operation within 438 clock cycles.Our design has a good performance in cycle-area products.
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efficient hardware implementation of mq Asymmetric Cipher pmi on fpgas
Information Security Practice and Experience, 2014Co-Authors: Shaohua Tang, Guomin Chen, Zhiniang PengAbstract:PMI+ is a Multivariate Quadratic (MQ) public key algorithm used for encryption and decryption operations, and belongs to post quantum cryptography. We designs a hardware on FPGAs to efficiently implement PMI+ in this paper. Our main contributions are that, firstly, a hardware architecture of encryption and decryption of PMI+ is developed, and description of corresponding hardware algorithm is proposed; secondly, basic arithmetic units are implemented with higher efficiency that multiplication, squaring, vector dot product and power operation are implemented in full parallel; and thirdly, an optimized implementation for core module, including optimized large power operation, is achieved. The encryption and decryption hardware of PMI+ is efficiently realized on FPGA by the above optimization and improvement. It is verified by experiments that the designed hardware can complete an encryption operation within 497 clock cycles, and the clock frequency can be up to 145.6MHz, and the designed hardware can complete a decryption operation within 438 clock cycles wherein the clock frequency can be up to 37.04MHz.
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ISPEC - Efficient Hardware Implementation of MQ Asymmetric Cipher PMI+ on FPGAs
Information Security Practice and Experience, 2014Co-Authors: Shaohua Tang, Guomin Chen, Zhiniang PengAbstract:PMI+ is a Multivariate Quadratic (MQ) public key algorithm used for encryption and decryption operations, and belongs to post quantum cryptography. We designs a hardware on FPGAs to efficiently implement PMI+ in this paper. Our main contributions are that, firstly, a hardware architecture of encryption and decryption of PMI+ is developed, and description of corresponding hardware algorithm is proposed; secondly, basic arithmetic units are implemented with higher efficiency that multiplication, squaring, vector dot product and power operation are implemented in full parallel; and thirdly, an optimized implementation for core module, including optimized large power operation, is achieved. The encryption and decryption hardware of PMI+ is efficiently realized on FPGA by the above optimization and improvement. It is verified by experiments that the designed hardware can complete an encryption operation within 497 clock cycles, and the clock frequency can be up to 145.6MHz, and the designed hardware can complete a decryption operation within 438 clock cycles wherein the clock frequency can be up to 37.04MHz.
Xiaofeng Chen - One of the best experts on this subject based on the ideXlab platform.
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Efficient hardware implementation of PMI+ for low-resource devices in mobile cloud computing
Future Generation Computer Systems, 2015Co-Authors: Shaohua Tang, Guomin Chen, Zhiniang Peng, Adama Diene, Xiaofeng ChenAbstract:With rapid development of cloud computing, security issues have gained more and more attention, especially in mobile cloud computing environment. Smart phones and other mobile devices provide a lot of convenience to us, but due to its intrinsic low-resource limitation, it also causes many security problems. In this paper, we design a hardware that can efficiently implement PMI+, which is a Multivariate Quadratic (MQ) Asymmetric Cipher, for low-resource devices in mobile cloud computing. Our main contributions are that, firstly, hardware architectures of encryption and decryption of PMI+ are developed, and descriptions of corresponding hardware algorithm are proposed; secondly, basic arithmetic units are implemented with higher efficiency that multiplication, squaring, vector dot product and power operation are implemented in full parallel; and thirdly, optimized implementations for core modules, including optimized large power operation, are achieved. The encryption and decryption hardware of PMI+ is efficiently realized on FPGA by the above optimization and improvement. It is verified by experiments that the designed hardware can complete an encryption operation within 497 clock cycles, and the clock frequency can be up to 145.60 MHz, and the designed hardware can complete a decryption operation within 438 clock cycles wherein the clock frequency can be up to 132.21 MHz. Our experiment results also confirm that our design can be deployed in low-resource devices as thin client of mobile cloud computing. We design a hardware to implement MQ Asymmetric Cipher PMI+ for low-resource devices.Basic arithmetic units are implemented in optimized and full parallel.Our design can complete a large power operation in 16 clock cycles.Our hardware can complete an encryption operation of PMI+ within 497 clock cycles, and a decryption operation within 438 clock cycles.Our design has a good performance in cycle-area products.
Aleksejus Mihalkovich - One of the best experts on this subject based on the ideXlab platform.
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investigation of matrix power Asymmetric Cipher resistant to linear algebra attack
International Conference on Information and Software Technologies, 2019Co-Authors: Aleksejus Mihalkovich, Matas LevinskasAbstract:This paper continues our research of the so-called matrix power function and its application to cryptography. We consider the simplest case of the improved matrix power Asymmetric cypher (MPAC). We show that our protocol is resistant to linear algebra attack, which can be applied to the initial version of MPAC to break it in polynomial time. Our main goal is to present the general idea for the choice of public parameters of MPAC protocol to avoid this attack while also avoiding exhaustive search attack.
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ICIST - Investigation of Matrix Power Asymmetric Cipher Resistant to Linear Algebra Attack
Communications in Computer and Information Science, 2019Co-Authors: Aleksejus Mihalkovich, Matas LevinskasAbstract:This paper continues our research of the so-called matrix power function and its application to cryptography. We consider the simplest case of the improved matrix power Asymmetric cypher (MPAC). We show that our protocol is resistant to linear algebra attack, which can be applied to the initial version of MPAC to break it in polynomial time. Our main goal is to present the general idea for the choice of public parameters of MPAC protocol to avoid this attack while also avoiding exhaustive search attack.
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Improved Asymmetric Cipher Based on Matrix Power Function with Provable Security
Symmetry, 2017Co-Authors: Eligijus Sakalauskas, Aleksejus Mihalkovich, Algimantas VenčkauskasAbstract:The improved version of the author’s previously declared Asymmetric Cipher protocol based on matrix power function (MPF) is presented. Proposed modification avoids discrete logarithm attack (DLA) which could be applied to the previously declared protocol. This attack allows us to transform the initial system of MPF equations to so-called matrix multivariate quadratic (MMQ) system of equations, which is a system representing a subclass of multivariate quadratic (MQ) systems of equations. We are making a conjecture that avoidance of DLA in protocol, presented here, should increase its security, since an attempt to solve the initial system of MPF equations would appear to be no less complex than solving the system of MMQ equations. No algorithms are known to solve such a system of equations. Security parameters and their secure values are defined. Security analysis against chosen plaintext attack (CPA) and chosen Ciphertext attack (CCA) is presented. Measures taken to prevent DLA attack increase the security of this protocol with respect to the previously declated protocol.
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New Asymmetric Cipher of Non-Commuting Cryptography Class Based on Matrix Power Function
Informatica, 2014Co-Authors: Eligijus Sakalauskas, Aleksejus MihalkovichAbstract:New Asymmetric Cipher based on matrix power function is presented. Cipher belongs to the class of recently intensively evolving non-commuting cryptography due to expectation of its resistance to potential quantum cryptanalysis. The algebraic structures for proposed Cipher construction are defined. Security analysis was per- formed and security parameters are defined. On the base of this research the secure parameters values are determined. The comparison of efficiency of microprocessor realization of proposed algorithm with different security parameters values is presented.
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New Asymmetric Cipher Based On Matrix Power Function and Its Implementation in Microprocessors Efficiency Investigation
Electronics and Electrical Engineering, 2013Co-Authors: Aleksejus Mihalkovich, Eligijus Sakalauskas, Algimantas VenčkauskasAbstract:The efficiency of realization of a new Asymmetric Cipher in microprocessors is presented. The Cipher is based on the matrix power function and therefore to the contrary of traditional Asymmetric Ciphers the computation with large numbers is avoided. Since microprocessors are widely used in embedded systems such as smart-cards and have restricted computational resources the development of effectively realizable cryptographic primitives is a very actual problem. The efficiency investigation of proposed Cipher showed that it has a significant superiority with respect to the traditional Asymmetric Ciphers such as El-Gamal and elliptic curves. DOI: http://dx.doi.org/10.5755/j01.eee.19.10.5906
