The Experts below are selected from a list of 1383 Experts worldwide ranked by ideXlab platform

Alexander Zeier - One of the best experts on this subject based on the ideXlab platform.

  • ensuring service Backwards Compatibility with generic web services
    Principles of Engineering Service-Oriented Systems, 2009
    Co-Authors: Vadym Borovskiy, Juergen Mueller, Matthieupatrick Schapranow, Alexander Zeier
    Abstract:

    Ensuring Compatibility in service-oriented systems is a challenging task. This article addresses the challenge of maintaining Web service Backwards Compatibility. In particular, the authors suggest a new interface design technique called Generic Web Services that allows service providers to add new features to Web services without breaking Compatibility with existing clients. This is achieved by partially shifting the semantics of service operations from design time to runtime by relaxing the operations signatures with identity parameters. Furthermore, the authors discuss the advantages and disadvantages of generic Web services. The article also contains an example that applies the aforementioned technique to a Web service from SAP Enterprise Services Workplace.

  • PESOS@ICSE - Ensuring service Backwards Compatibility with Generic Web Services
    2009 ICSE Workshop on Principles of Engineering Service Oriented Systems, 2009
    Co-Authors: Vadym Borovskiy, Juergen Mueller, Matthieupatrick Schapranow, Alexander Zeier
    Abstract:

    Ensuring Compatibility in service-oriented systems is a challenging task. This article addresses the challenge of maintaining Web service Backwards Compatibility. In particular, the authors suggest a new interface design technique called Generic Web Services that allows service providers to add new features to Web services without breaking Compatibility with existing clients. This is achieved by partially shifting the semantics of service operations from design time to runtime by relaxing the operations signatures with identity parameters. Furthermore, the authors discuss the advantages and disadvantages of generic Web services. The article also contains an example that applies the aforementioned technique to a Web service from SAP Enterprise Services Workplace.

  • ICWS - Generic Web Services Extensible Functionality with Stable Interface
    2009 IEEE International Conference on Web Services, 2009
    Co-Authors: Vadym Borovskiy, Sebastian Enderlein, Alexander Zeier
    Abstract:

    Extending the functionality of Web services without invalidating the code of existing clients has been a challenging task. This paper proposes a new interface design technique called "Generic Web Services" that preserves a service's Backwards Compatibility while enriching its functionality. This is accomplished by applying interface relaxation technique - shifting the semantics of a service's API from design time to runtime by using identity parameters. The paper gives an example illustrating the idea on a Web service from SAP Enterprise Services Workplace.

Vijay Nagarajan - One of the best experts on this subject based on the ideXlab platform.

  • rc3 consistency directed cache coherence for x86 64 with rc extensions
    International Conference on Parallel Architectures and Compilation Techniques, 2015
    Co-Authors: Marco Elver, Vijay Nagarajan
    Abstract:

    The recent convergence towards programming language based memory consistency models has sparked renewed interest in lazy cache coherence protocols. These protocols exploit synchronization information by enforcing coherence only at synchronization boundaries via self-invalidation. In effect, such protocols do not require sharer tracking which benefits scalability. On the downside, such protocols are only readily applicable to a restricted set of consistency models, such as Release Consistency (RC), which expose synchronization information explicitly. In particular, existing architectures with stricter consistency models (such as x86-64) cannot readily make use of lazy coherence protocols without either: changing the architecture's consistency model to (a variant of) RC at the expense of Backwards Compatibility, or adapting the protocol to satisfy the stricter consistency model, thereby failing to benefit from synchronization information. We show an approach for the x86-64 architecture, which is a compromise between the two. First, we propose a mechanism to convey synchronization information via a simple ISA extension, while retaining Backwards Compatibility with legacy codes and older microarchitectures. Second, we propose RC3, a scalable hardware cache coherence protocol for RCtso, the resulting memory consistency model. RC3 does not track sharers, and relies on self-invalidation on acquires. To satisfy RCtso efficiently, the protocol reduces self-invalidations transitively using per-L1 timestamps only. RC3 outperforms a conventional lazy RC protocol by 12%, achieving performance comparable to a MESI directory protocol for RC optimized programs. RC3's storage overhead per cache line scales logarithmically with increasing core count, and reduces on-chip coherence storage overheads by 45% compared to a related approach specifically targeting TSO.

  • PACT - RC3: Consistency Directed Cache Coherence for x86-64 with RC Extensions
    2015 International Conference on Parallel Architecture and Compilation (PACT), 2015
    Co-Authors: Marco Elver, Vijay Nagarajan
    Abstract:

    The recent convergence towards programming language based memory consistency models has sparked renewed interest in lazy cache coherence protocols. These protocols exploit synchronization information by enforcing coherence only at synchronization boundaries via self-invalidation. In effect, such protocols do not require sharer tracking which benefits scalability. On the downside, such protocols are only readily applicable to a restricted set of consistency models, such as Release Consistency (RC), which expose synchronization information explicitly. In particular, existing architectures with stricter consistency models (such as x86-64) cannot readily make use of lazy coherence protocols without either: changing the architecture's consistency model to (a variant of) RC at the expense of Backwards Compatibility, or adapting the protocol to satisfy the stricter consistency model, thereby failing to benefit from synchronization information. We show an approach for the x86-64 architecture, which is a compromise between the two. First, we propose a mechanism to convey synchronization information via a simple ISA extension, while retaining Backwards Compatibility with legacy codes and older microarchitectures. Second, we propose RC3, a scalable hardware cache coherence protocol for RCtso, the resulting memory consistency model. RC3 does not track sharers, and relies on self-invalidation on acquires. To satisfy RCtso efficiently, the protocol reduces self-invalidations transitively using per-L1 timestamps only. RC3 outperforms a conventional lazy RC protocol by 12%, achieving performance comparable to a MESI directory protocol for RC optimized programs. RC3's storage overhead per cache line scales logarithmically with increasing core count, and reduces on-chip coherence storage overheads by 45% compared to a related approach specifically targeting TSO.

Vadym Borovskiy - One of the best experts on this subject based on the ideXlab platform.

  • ensuring service Backwards Compatibility with generic web services
    Principles of Engineering Service-Oriented Systems, 2009
    Co-Authors: Vadym Borovskiy, Juergen Mueller, Matthieupatrick Schapranow, Alexander Zeier
    Abstract:

    Ensuring Compatibility in service-oriented systems is a challenging task. This article addresses the challenge of maintaining Web service Backwards Compatibility. In particular, the authors suggest a new interface design technique called Generic Web Services that allows service providers to add new features to Web services without breaking Compatibility with existing clients. This is achieved by partially shifting the semantics of service operations from design time to runtime by relaxing the operations signatures with identity parameters. Furthermore, the authors discuss the advantages and disadvantages of generic Web services. The article also contains an example that applies the aforementioned technique to a Web service from SAP Enterprise Services Workplace.

  • PESOS@ICSE - Ensuring service Backwards Compatibility with Generic Web Services
    2009 ICSE Workshop on Principles of Engineering Service Oriented Systems, 2009
    Co-Authors: Vadym Borovskiy, Juergen Mueller, Matthieupatrick Schapranow, Alexander Zeier
    Abstract:

    Ensuring Compatibility in service-oriented systems is a challenging task. This article addresses the challenge of maintaining Web service Backwards Compatibility. In particular, the authors suggest a new interface design technique called Generic Web Services that allows service providers to add new features to Web services without breaking Compatibility with existing clients. This is achieved by partially shifting the semantics of service operations from design time to runtime by relaxing the operations signatures with identity parameters. Furthermore, the authors discuss the advantages and disadvantages of generic Web services. The article also contains an example that applies the aforementioned technique to a Web service from SAP Enterprise Services Workplace.

  • ICWS - Generic Web Services Extensible Functionality with Stable Interface
    2009 IEEE International Conference on Web Services, 2009
    Co-Authors: Vadym Borovskiy, Sebastian Enderlein, Alexander Zeier
    Abstract:

    Extending the functionality of Web services without invalidating the code of existing clients has been a challenging task. This paper proposes a new interface design technique called "Generic Web Services" that preserves a service's Backwards Compatibility while enriching its functionality. This is accomplished by applying interface relaxation technique - shifting the semantics of a service's API from design time to runtime by using identity parameters. The paper gives an example illustrating the idea on a Web service from SAP Enterprise Services Workplace.

Marco Elver - One of the best experts on this subject based on the ideXlab platform.

  • rc3 consistency directed cache coherence for x86 64 with rc extensions
    International Conference on Parallel Architectures and Compilation Techniques, 2015
    Co-Authors: Marco Elver, Vijay Nagarajan
    Abstract:

    The recent convergence towards programming language based memory consistency models has sparked renewed interest in lazy cache coherence protocols. These protocols exploit synchronization information by enforcing coherence only at synchronization boundaries via self-invalidation. In effect, such protocols do not require sharer tracking which benefits scalability. On the downside, such protocols are only readily applicable to a restricted set of consistency models, such as Release Consistency (RC), which expose synchronization information explicitly. In particular, existing architectures with stricter consistency models (such as x86-64) cannot readily make use of lazy coherence protocols without either: changing the architecture's consistency model to (a variant of) RC at the expense of Backwards Compatibility, or adapting the protocol to satisfy the stricter consistency model, thereby failing to benefit from synchronization information. We show an approach for the x86-64 architecture, which is a compromise between the two. First, we propose a mechanism to convey synchronization information via a simple ISA extension, while retaining Backwards Compatibility with legacy codes and older microarchitectures. Second, we propose RC3, a scalable hardware cache coherence protocol for RCtso, the resulting memory consistency model. RC3 does not track sharers, and relies on self-invalidation on acquires. To satisfy RCtso efficiently, the protocol reduces self-invalidations transitively using per-L1 timestamps only. RC3 outperforms a conventional lazy RC protocol by 12%, achieving performance comparable to a MESI directory protocol for RC optimized programs. RC3's storage overhead per cache line scales logarithmically with increasing core count, and reduces on-chip coherence storage overheads by 45% compared to a related approach specifically targeting TSO.

  • PACT - RC3: Consistency Directed Cache Coherence for x86-64 with RC Extensions
    2015 International Conference on Parallel Architecture and Compilation (PACT), 2015
    Co-Authors: Marco Elver, Vijay Nagarajan
    Abstract:

    The recent convergence towards programming language based memory consistency models has sparked renewed interest in lazy cache coherence protocols. These protocols exploit synchronization information by enforcing coherence only at synchronization boundaries via self-invalidation. In effect, such protocols do not require sharer tracking which benefits scalability. On the downside, such protocols are only readily applicable to a restricted set of consistency models, such as Release Consistency (RC), which expose synchronization information explicitly. In particular, existing architectures with stricter consistency models (such as x86-64) cannot readily make use of lazy coherence protocols without either: changing the architecture's consistency model to (a variant of) RC at the expense of Backwards Compatibility, or adapting the protocol to satisfy the stricter consistency model, thereby failing to benefit from synchronization information. We show an approach for the x86-64 architecture, which is a compromise between the two. First, we propose a mechanism to convey synchronization information via a simple ISA extension, while retaining Backwards Compatibility with legacy codes and older microarchitectures. Second, we propose RC3, a scalable hardware cache coherence protocol for RCtso, the resulting memory consistency model. RC3 does not track sharers, and relies on self-invalidation on acquires. To satisfy RCtso efficiently, the protocol reduces self-invalidations transitively using per-L1 timestamps only. RC3 outperforms a conventional lazy RC protocol by 12%, achieving performance comparable to a MESI directory protocol for RC optimized programs. RC3's storage overhead per cache line scales logarithmically with increasing core count, and reduces on-chip coherence storage overheads by 45% compared to a related approach specifically targeting TSO.

Parag Kulkarni - One of the best experts on this subject based on the ideXlab platform.

  • Simultaneous transmit and receive operation in next generation ieee 802.11 wlans: A mac protocol design approach
    IEEE Wireless Communications, 2017
    Co-Authors: Adnan Aijaz, Parag Kulkarni
    Abstract:

    Full-duplex (FD) technology is likely to be adopted in various legacy communications standards. The IEEE 802.11ax working group has been considering a simultaneous transmit and receive (STR) mode for the next generation wireless local area networks (WLANs). Enabling STR mode (FD communication mode) in 802.11 networks creates bi-directional FD (BFD) and uni-directional FD (UFD) links. The key challenge is to integrate STR mode with minimal protocol modifications, while considering the co-existence of FD and legacy half-duplex (HD) stations (STAs) and Backwards Compatibility. This paper proposes a simple and practical approach to enable STR mode in 802.11 networks with co-existing FD and HD STAs. The protocol explicitly accounts for the peculiarities of FD environments and Backwards Compatibility. Key aspects of the proposed solution include FD capability discovery, handshake mechanism for channel access, node selection for UFD transmission, adaptive acknowledgement (ACK) timeout for STAs engaged in BFD or UFD transmission, and mitigation of contention unfairness. Performance evaluation demonstrates the effectiveness of the proposed solution in realizing the gains of FD technology for next generation WLANs.