The Experts below are selected from a list of 108 Experts worldwide ranked by ideXlab platform
Pou-chu Chou - One of the best experts on this subject based on the ideXlab platform.
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Cascaded Feedforward Sigma-delta Modulator for Wide Bandwidth Applications
2001Co-Authors: Jen-shiun Chiang, Teng-hung Chang, Pou-chu ChouAbstract:ABSTRACT A new sigma-delta modulator architecture for wide Bandwidth Application called cascaded feedforward sigma-delta modulator is proposed in this paper. This sigma-delta modulator is similar to the conventional feedforward summation sigma-delta modulator. The conventional feedforward summation sigma-delta modulator uses multi-bit feedback and therefore a multi-bit digital-to-analog converter (DAC) is needed. Due to the nonlinearity of the multi-bit DAC, it is difficult to be implemented. On the other hand the proposed approach uses 1.5-bit feedback, and thus the implementation of the analog part is much easier than the conventional one. Since the 1.5-bit feedback will cause coarse quantization errors, error cancellation must be done in the digital part. Here an adaptive filter with least mean square algorithm is used to reduce the nonlinear effect. The simulation results show that the signal to noise plus distortion ratio (SNDR) of this architecture is very close to that of the ideal feedforward summation sigma-delta modulator with multi-bit DAC and can be used for the wide Bandwidth Application.
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ICECS - Cascaded feedforward sigma-delta modulator for wide Bandwidth Applications
ICECS 2001. 8th IEEE International Conference on Electronics Circuits and Systems (Cat. No.01EX483), 1Co-Authors: Jen-shiun Chiang, Pou-chu Chou, Teng-hung ChangAbstract:In this paper, we propose a cascaded feedforward sigma-delta modulator for wide Bandwidth Applications. In our proposed approach, we use a 1.5-bit quantizer as feedback in the multi-bit sigma-delta modulator. The 1.5-bit feedback may cause coarse quantization errors, however the error can be canceled in the digital part. Here an adaptive filter with least mean square algorithm is used to reduce the nonlinear effect. The simulation results show that the SNDR of this architecture is very close to that of the ideal feedforward summation sigma-delta modulator with multi-bit DAC and can be used for the wide Bandwidth Application.
Teng-hung Chang - One of the best experts on this subject based on the ideXlab platform.
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Cascaded Feedforward Sigma-delta Modulator for Wide Bandwidth Applications
2001Co-Authors: Jen-shiun Chiang, Teng-hung Chang, Pou-chu ChouAbstract:ABSTRACT A new sigma-delta modulator architecture for wide Bandwidth Application called cascaded feedforward sigma-delta modulator is proposed in this paper. This sigma-delta modulator is similar to the conventional feedforward summation sigma-delta modulator. The conventional feedforward summation sigma-delta modulator uses multi-bit feedback and therefore a multi-bit digital-to-analog converter (DAC) is needed. Due to the nonlinearity of the multi-bit DAC, it is difficult to be implemented. On the other hand the proposed approach uses 1.5-bit feedback, and thus the implementation of the analog part is much easier than the conventional one. Since the 1.5-bit feedback will cause coarse quantization errors, error cancellation must be done in the digital part. Here an adaptive filter with least mean square algorithm is used to reduce the nonlinear effect. The simulation results show that the signal to noise plus distortion ratio (SNDR) of this architecture is very close to that of the ideal feedforward summation sigma-delta modulator with multi-bit DAC and can be used for the wide Bandwidth Application.
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ICECS - Cascaded feedforward sigma-delta modulator for wide Bandwidth Applications
ICECS 2001. 8th IEEE International Conference on Electronics Circuits and Systems (Cat. No.01EX483), 1Co-Authors: Jen-shiun Chiang, Pou-chu Chou, Teng-hung ChangAbstract:In this paper, we propose a cascaded feedforward sigma-delta modulator for wide Bandwidth Applications. In our proposed approach, we use a 1.5-bit quantizer as feedback in the multi-bit sigma-delta modulator. The 1.5-bit feedback may cause coarse quantization errors, however the error can be canceled in the digital part. Here an adaptive filter with least mean square algorithm is used to reduce the nonlinear effect. The simulation results show that the SNDR of this architecture is very close to that of the ideal feedforward summation sigma-delta modulator with multi-bit DAC and can be used for the wide Bandwidth Application.
Jen-shiun Chiang - One of the best experts on this subject based on the ideXlab platform.
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Cascaded Feedforward Sigma-delta Modulator for Wide Bandwidth Applications
2001Co-Authors: Jen-shiun Chiang, Teng-hung Chang, Pou-chu ChouAbstract:ABSTRACT A new sigma-delta modulator architecture for wide Bandwidth Application called cascaded feedforward sigma-delta modulator is proposed in this paper. This sigma-delta modulator is similar to the conventional feedforward summation sigma-delta modulator. The conventional feedforward summation sigma-delta modulator uses multi-bit feedback and therefore a multi-bit digital-to-analog converter (DAC) is needed. Due to the nonlinearity of the multi-bit DAC, it is difficult to be implemented. On the other hand the proposed approach uses 1.5-bit feedback, and thus the implementation of the analog part is much easier than the conventional one. Since the 1.5-bit feedback will cause coarse quantization errors, error cancellation must be done in the digital part. Here an adaptive filter with least mean square algorithm is used to reduce the nonlinear effect. The simulation results show that the signal to noise plus distortion ratio (SNDR) of this architecture is very close to that of the ideal feedforward summation sigma-delta modulator with multi-bit DAC and can be used for the wide Bandwidth Application.
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ICECS - Cascaded feedforward sigma-delta modulator for wide Bandwidth Applications
ICECS 2001. 8th IEEE International Conference on Electronics Circuits and Systems (Cat. No.01EX483), 1Co-Authors: Jen-shiun Chiang, Pou-chu Chou, Teng-hung ChangAbstract:In this paper, we propose a cascaded feedforward sigma-delta modulator for wide Bandwidth Applications. In our proposed approach, we use a 1.5-bit quantizer as feedback in the multi-bit sigma-delta modulator. The 1.5-bit feedback may cause coarse quantization errors, however the error can be canceled in the digital part. Here an adaptive filter with least mean square algorithm is used to reduce the nonlinear effect. The simulation results show that the SNDR of this architecture is very close to that of the ideal feedforward summation sigma-delta modulator with multi-bit DAC and can be used for the wide Bandwidth Application.
Chih-pin Hung - One of the best experts on this subject based on the ideXlab platform.
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High Bandwidth Application on 2.5D IC silicon interposer
2014 15th International Conference on Electronic Packaging Technology, 2014Co-Authors: Chen-chao Wang, Hung-hsiang Cheng, Ming-feng Chung, Cheng-yu Ho, Chi-tsung Chiu, Chih-pin HungAbstract:A potential technology by silicon interposer enables high Bandwidth and low power Application processing devices of the future, because the demand of smart mobile products are driving for higher logic-to-memory Bandwidth (BW) over 30 GB/s with lower power consumption and ultra-memory capacity. This paper presents a 2.5D-IC structure with silicon interposer to demonstrate electrical performances including signal integrity (SI) and power integrity (PI) by using WideIO memory interface. Of course, the accuracy of TSV has demonstrated by measurement as well.
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High Bandwidth Application with Wide I/O memory on 2.5D-IC silicon interposer
2013 3rd IEEE CPMT Symposium Japan, 2013Co-Authors: Chen-chao Wang, Hung-hsiang Cheng, Ming-feng Chung, Chi-tsung Chiu, Po-chih Pan, Chih-pin HungAbstract:A potential technology by silicon interposer enables high Bandwidth and low power Application processing devices of the future, because the demand of smart mobile products are driving for higher logic-to-memory Bandwidth (BW) over 30 GB/s with lower power consumption and ultra-memory capacity. This paper presents a 2.5D-IC structure with silicon interposer to demonstrate electrical performances including signal integrity (SI) and power integrity (PI) by using WideIO memory interface. Of course, the accuracy of TSV has demonstrated by measurement as well.
Chen-chao Wang - One of the best experts on this subject based on the ideXlab platform.
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High Bandwidth Application on 2.5D IC silicon interposer
2014 15th International Conference on Electronic Packaging Technology, 2014Co-Authors: Chen-chao Wang, Hung-hsiang Cheng, Ming-feng Chung, Cheng-yu Ho, Chi-tsung Chiu, Chih-pin HungAbstract:A potential technology by silicon interposer enables high Bandwidth and low power Application processing devices of the future, because the demand of smart mobile products are driving for higher logic-to-memory Bandwidth (BW) over 30 GB/s with lower power consumption and ultra-memory capacity. This paper presents a 2.5D-IC structure with silicon interposer to demonstrate electrical performances including signal integrity (SI) and power integrity (PI) by using WideIO memory interface. Of course, the accuracy of TSV has demonstrated by measurement as well.
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High Bandwidth Application with Wide I/O memory on 2.5D-IC silicon interposer
2013 3rd IEEE CPMT Symposium Japan, 2013Co-Authors: Chen-chao Wang, Hung-hsiang Cheng, Ming-feng Chung, Chi-tsung Chiu, Po-chih Pan, Chih-pin HungAbstract:A potential technology by silicon interposer enables high Bandwidth and low power Application processing devices of the future, because the demand of smart mobile products are driving for higher logic-to-memory Bandwidth (BW) over 30 GB/s with lower power consumption and ultra-memory capacity. This paper presents a 2.5D-IC structure with silicon interposer to demonstrate electrical performances including signal integrity (SI) and power integrity (PI) by using WideIO memory interface. Of course, the accuracy of TSV has demonstrated by measurement as well.
