The Experts below are selected from a list of 25722 Experts worldwide ranked by ideXlab platform
Mehrdad Nourani - One of the best experts on this subject based on the ideXlab platform.
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DATE - Extending JTAG for Testing Signal Integrity in SoCs
2003 Design Automation and Test in Europe Conference and Exhibition, 2003Co-Authors: Nisar Ahmed, M.h. Tehranipour, Mehrdad NouraniAbstract:As the technology is shrinking and the working frequency is going into the multi Gigahertz range, the issues related to interconnect testing are becoming more dominant. Specifically, Signal Integrity loss issues are becoming more important, and detection and diagnosis of these losses are becoming a great challenge. In this paper, an enhanced boundary scan architecture, with slight modification in the boundary scan cells, is proposed to test Signal Integrity in SoC interconnects. Our extended JTAG architecture: 1) minimizes scan-in operation by using modified boundary scan cells in pattern generation; and 2) incorporates the Integrity loss information within the modified observation cells. To fully comply with the JTAG standard, we propose two new instructions, one for pattern generation and the other for scanning out the captured Signal Integrity information.
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built in self test for Signal Integrity
Design Automation Conference, 2001Co-Authors: Mehrdad Nourani, Amir AttarhaAbstract:Unacceptable loss of Signal Integrity may harm the functionality of SoCs permanently or intermittently. We propose a systematic approach to model and test Signal Integrity in deep-submicron high-speed interconnects. Various Signal Integrity problems occurring on such interconnects (e.g. crosstalk, overshoot, noise, skew, etc.) are considered in a unified model. We also present a test methodology that uses a noise detection circuitry to detect low Integrity Signals and an inexpensive test architecture to measure and read the statistics for final observation and analysis.
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DATE - Extending JTAG for Testing Signal Integrity in SoCs
2003 Design Automation and Test in Europe Conference and Exhibition, 1Co-Authors: Nisar Ahmed, M.h. Tehranipour, Mehrdad NouraniAbstract:As the technology is shrinking and the working frequency is going into multi gigahertz range, the issues related to interconnect testing are becoming more dominant. Specifically, Signal Integrity loss issues are becoming more important and detection and diagnosis of these losses are becoming a great challenge. In this paper, an enhanced boundary scan architecture with slight modification in the boundary scan cells is proposed to test Signal Integrity in SoC interconnects. Our extended JTAG architecture: 1) minimizes scan-in operation by using modified boundary scan cells in pattern generation; and 2) incorporates the Integrity loss information within the modified observation cells. To fully comply with JTAG standard, we propose two new instructions, one for pattern generation and the other for scanning out the captured Signal Integrity information.
Nisar Ahmed - One of the best experts on this subject based on the ideXlab platform.
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DATE - Extending JTAG for Testing Signal Integrity in SoCs
2003 Design Automation and Test in Europe Conference and Exhibition, 2003Co-Authors: Nisar Ahmed, M.h. Tehranipour, Mehrdad NouraniAbstract:As the technology is shrinking and the working frequency is going into the multi Gigahertz range, the issues related to interconnect testing are becoming more dominant. Specifically, Signal Integrity loss issues are becoming more important, and detection and diagnosis of these losses are becoming a great challenge. In this paper, an enhanced boundary scan architecture, with slight modification in the boundary scan cells, is proposed to test Signal Integrity in SoC interconnects. Our extended JTAG architecture: 1) minimizes scan-in operation by using modified boundary scan cells in pattern generation; and 2) incorporates the Integrity loss information within the modified observation cells. To fully comply with the JTAG standard, we propose two new instructions, one for pattern generation and the other for scanning out the captured Signal Integrity information.
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DATE - Extending JTAG for Testing Signal Integrity in SoCs
2003 Design Automation and Test in Europe Conference and Exhibition, 1Co-Authors: Nisar Ahmed, M.h. Tehranipour, Mehrdad NouraniAbstract:As the technology is shrinking and the working frequency is going into multi gigahertz range, the issues related to interconnect testing are becoming more dominant. Specifically, Signal Integrity loss issues are becoming more important and detection and diagnosis of these losses are becoming a great challenge. In this paper, an enhanced boundary scan architecture with slight modification in the boundary scan cells is proposed to test Signal Integrity in SoC interconnects. Our extended JTAG architecture: 1) minimizes scan-in operation by using modified boundary scan cells in pattern generation; and 2) incorporates the Integrity loss information within the modified observation cells. To fully comply with JTAG standard, we propose two new instructions, one for pattern generation and the other for scanning out the captured Signal Integrity information.
Amir Attarha - One of the best experts on this subject based on the ideXlab platform.
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built in self test for Signal Integrity
Design Automation Conference, 2001Co-Authors: Mehrdad Nourani, Amir AttarhaAbstract:Unacceptable loss of Signal Integrity may harm the functionality of SoCs permanently or intermittently. We propose a systematic approach to model and test Signal Integrity in deep-submicron high-speed interconnects. Various Signal Integrity problems occurring on such interconnects (e.g. crosstalk, overshoot, noise, skew, etc.) are considered in a unified model. We also present a test methodology that uses a noise detection circuitry to detect low Integrity Signals and an inexpensive test architecture to measure and read the statistics for final observation and analysis.
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DAC - Built-in self-test for Signal Integrity
Proceedings of the 38th conference on Design automation - DAC '01, 2001Co-Authors: Amir AttarhaAbstract:Unacceptable loss of Signal Integrity may harm the functionality of SoCs permanently or intermittently. We propose a systematic approach to model and test Signal Integrity in deep-submicron high-speed interconnects. Various Signal Integrity problems occurring on such interconnects (e.g. crosstalk, overshoot, noise, skew, etc.) are considered in a unified model. We also present a test methodology that uses a noise detection circuitry to detect low Integrity Signals and an inexpensive test architecture to measure and read the statistics for final observation and analysis.
Chunfei Ye - One of the best experts on this subject based on the ideXlab platform.
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Transmission lines and Signal Integrity fundamentals
2017 IEEE International Symposium on Electromagnetic Compatibility & Signal Power Integrity (EMCSI), 2017Co-Authors: Xiaoning Ye, Chunfei YeAbstract:• Signal Integrity is increasingly challenging as data rate increases – form factor – cost • Some critical aspects of Signal Integrity are discussed and mitigation strategies presented – Loss, impedance matching, crosstalk, etc. • Non-ideal effects of interconnect need to be taken into account in high speed interconnect design • Equalization, Jitter, Eye-diagram are critical Signal Integrity fundamental concepts
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Fundamentals of Signal Integrity — for computing and communication systems
2017 IEEE International Symposium on Electromagnetic Compatibility & Signal Power Integrity (EMCSI), 2017Co-Authors: Chunfei YeAbstract:Summary • Signal Integrity is increasingly challenging as data rate increases – Form factor – Cost • Some critical aspects of Signal Integrity are discussed and mitigation strategies presented – Loss, impedance matching, crosstalk, etc. • Non-ideal effects of interconnect need to be taken into account in high speed interconnect design
Kraig Mitzner - One of the best experts on this subject based on the ideXlab platform.
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Signal Integrity simulation with OrCAD
Complete PCB Design Using OrCAD Capture and PCB Editor, 2019Co-Authors: Kraig Mitzner, Bob Doe, Alexander Akulin, Anton Suponin, Dirk MüllerAbstract:Abstract Signal Integrity or “SI” is a measure of the quality of electrical Signals sent from driver to receiver. Deep explanation of SI terms and issues is provided in Chapter 6, Printed circuit board design for Signal Integrity. Here we will explain briefly how the SI issues in your printed circuit board (PCB) design can be solved with the help of OrCAD Signal Explorer tool (which is included to the OrCAD Professional bundle), or with more powerful tools, such as OrCAD PCB SI, Sigrity ERC, or Sigrity Advanced SI/Advanced PI.
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PCB Design for Signal Integrity
Complete PCB Design Using OrCAD Capture and PCB Editor, 2009Co-Authors: Kraig MitznerAbstract:This chapter addresses the electrical aspect of Printed Circuit Board (PCB) design. Desirable electrical characteristics of a circuit and its PCB include low noise, low distortion, low cross talk, and low radiated emissions, and so on. The purpose of this chapter is to introduce the issues that cause PCB performance problems and how to route the PCB to minimize them and maximize Signal Integrity. An overview of Signal Integrity, electromagnetic interference, and electromagnetic compatibility is presented and applied directly to PCB design. There are three goals in designing PCBs for electrical performance and Signal Integrity: the PCB should be immune from interference from other systems; it should not produce emissions that cause problems for other systems; and it should demonstrate the desired Signal quality. A common factor relating these three issues is electromagnetic waves. Topics such as loop inductance, ground bounce, ground planes, characteristic impedance, reflections, and ringing are discussed. The idea of “the unseen schematic” (the PCB layout) and its role in circuit operation on the PCB is introduced. Look-up tables and equations are provided to determine required trace widths for current handling and impedance as well as required trace spacing for high-voltage designs and high-frequency designs. Various layer stack-up topographies for analog, digital, and mixed-Signal applications are also described. A demonstration on how to use PSpice to simulate transmission lines to aid in circuit design and PCB layout is also provided.
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Chapter 6 – PCB Design for Signal Integrity
Complete PCB Design Using OrCad Capture and Layout, 2007Co-Authors: Kraig MitznerAbstract:Publisher Summary This chapter explores the printed circuit board (PCB) design for Signal Integrity. There are a few desirable characteristics of a circuit and its PCB. These include low noise, low distortion, low cross talk, and low radiated emissions. This chapter discusses issues that cause PCB performance problems and explains how to route the PCB to minimize them and maximize Signal Integrity. There are four areas for electrical considerations when routing a PCB: placing parts, PCB layer stack-up, bypass capacitors, and trace width and spacing width. The chapter incorporates several illustrative figures for better clarification. The chapter also outlines some of the issues related to circuit design constraints. These constraints are primarily the responsibility of the circuit design engineer. Because the symptoms of poor circuit design can be confused with PCB design problems, the chapter lists some of these issues. These include noise, distortion, and frequency response..
