The Experts below are selected from a list of 237 Experts worldwide ranked by ideXlab platform
Kyihwan Park - One of the best experts on this subject based on the ideXlab platform.
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Vibration reduction control of a voice coil motor (VCM)-driven actuator for SPM applications
The International Journal of Advanced Manufacturing Technology, 2010Co-Authors: Jongkyu Jung, Woosub Youm, Kyihwan ParkAbstract:This paper presents vibration reduction control of a voice coil motor (VCM)-driven actuator for SPM applications. We had developed a VCM nanoscanner. The scanner has flexure hinges structure. However, the VCM nanoscanner has some problems of thermal drift and small damping compared to the PZT driven nanoscanner. Especially, the small damping coefficient of the VCM nanoscanner causes mechanical vibration when the control input signal is near to the resonance frequencies of the scanner. Additionally, disturbance to the VCM scanner and electronic noise in the sensor also causes the mechanical vibration when they are near to the resonant frequencies. The mechanical vibration reduces the servo bandwidth as well as the accuracy, which deteriorates the AFM image of the samples. We design input shaping prefilter to reduce the signal applied to the VCM nanoscanner and electronic noise in the sensor whose frequency is close to the resonant frequency of the VCM nanoscanner. We measure the time and frequency response of the VCM scanner without using the prefilter and with using the prefilter. Finally, the topology images of a Bare Wafer are measured and compared using the AFM.
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Vibration reduction control of a voice coil motor (VCM) nano scanner
International Journal of Precision Engineering and Manufacturing, 2009Co-Authors: Jongkyu Jung, Woosub Youm, Kyihwan ParkAbstract:This paper presents vibration reduction control of a voice coil motor (VCM) nano scanner. We had developed a VCM scanner. The scanner has flexure hinges structure. However, the VCM nano scanner has some problems of thermal drift and small damping compared to the PZT driven nano scanner. Especially, the small damping coefficient of the VCM scanner causes mechanical vibration when the control input signal is near to the resonance frequencies. Additionally, disturbance to the VCM scanner and electronic noise in the sensor also cause the mechanical vibration when they are near to the resonant frequencies. The mechanical vibration reduces the servo bandwidth as well as the accuracy, which deteriorates the AFM image of the samples. We design a pre-filter to reduce the signal applied to the VCM nano scanner and electronic noise in the sensor whose frequency is closed the resonant frequency of the VCM nano scanner. We measure the time and frequency response of the VCM scanner without using the pre-filter and with using the pre-filter. Finally, the topology images of a Bare Wafer are measured and compared using the AFM.
Jongkyu Jung - One of the best experts on this subject based on the ideXlab platform.
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Vibration reduction control of a voice coil motor (VCM)-driven actuator for SPM applications
The International Journal of Advanced Manufacturing Technology, 2010Co-Authors: Jongkyu Jung, Woosub Youm, Kyihwan ParkAbstract:This paper presents vibration reduction control of a voice coil motor (VCM)-driven actuator for SPM applications. We had developed a VCM nanoscanner. The scanner has flexure hinges structure. However, the VCM nanoscanner has some problems of thermal drift and small damping compared to the PZT driven nanoscanner. Especially, the small damping coefficient of the VCM nanoscanner causes mechanical vibration when the control input signal is near to the resonance frequencies of the scanner. Additionally, disturbance to the VCM scanner and electronic noise in the sensor also causes the mechanical vibration when they are near to the resonant frequencies. The mechanical vibration reduces the servo bandwidth as well as the accuracy, which deteriorates the AFM image of the samples. We design input shaping prefilter to reduce the signal applied to the VCM nanoscanner and electronic noise in the sensor whose frequency is close to the resonant frequency of the VCM nanoscanner. We measure the time and frequency response of the VCM scanner without using the prefilter and with using the prefilter. Finally, the topology images of a Bare Wafer are measured and compared using the AFM.
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Vibration reduction control of a voice coil motor (VCM) nano scanner
International Journal of Precision Engineering and Manufacturing, 2009Co-Authors: Jongkyu Jung, Woosub Youm, Kyihwan ParkAbstract:This paper presents vibration reduction control of a voice coil motor (VCM) nano scanner. We had developed a VCM scanner. The scanner has flexure hinges structure. However, the VCM nano scanner has some problems of thermal drift and small damping compared to the PZT driven nano scanner. Especially, the small damping coefficient of the VCM scanner causes mechanical vibration when the control input signal is near to the resonance frequencies. Additionally, disturbance to the VCM scanner and electronic noise in the sensor also cause the mechanical vibration when they are near to the resonant frequencies. The mechanical vibration reduces the servo bandwidth as well as the accuracy, which deteriorates the AFM image of the samples. We design a pre-filter to reduce the signal applied to the VCM nano scanner and electronic noise in the sensor whose frequency is closed the resonant frequency of the VCM nano scanner. We measure the time and frequency response of the VCM scanner without using the pre-filter and with using the pre-filter. Finally, the topology images of a Bare Wafer are measured and compared using the AFM.
Chang-ki Hong - One of the best experts on this subject based on the ideXlab platform.
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Effect of Slurry pH on Poly Silicon CMP
2011Co-Authors: Young-jae Kang, Bong-kyun Kang, Jin-goo Park, Yi-koan Hong, Bo-un Yoon, Chang-ki HongAbstract:, its higher reliability than Al gate materials, and its ability to be deposited conformally over steep topography. The shrinkage of devices below 100 nm requires more stringent and new CMP processes including poly silicon CMP. Poly silicon can be polished easily with similar pads and slurries as they are used for the planarization of silicon oxide. In this study, single crystal and poly silicon Wafers were polished as a function of pH in silica based slurry to understand and compare the polishing mechanism of silicon. The static and dynamic etch rates and removal rate were measured as a function of slurry pH (11 ~ 13). The friction force and polishing temperature were also measured at different pHs. The single crystal silicon (Bare silicon) showed higher removal rate than the poly silicon. However, higher friction force was measured on poly silicon Wafer than on Bare Wafer. Keywords: Poly silicon CMP, Single crystal silicon CMP, Etch rate, Removal rate, Friction force
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Effect of Slurry pH on Poly Silicon CMP
International Conference on Planarization CMP Technology, 2007Co-Authors: Young-jae Kang, Bong-kyun Kang, Jin-goo Park, Yi-koan Hong, Bo-un Yoon, Chang-ki HongAbstract:Heavily doped poly silicon films have been widely used as gate electrodes and interconnections in MOS circuits because of its compatibility with subsequent high temperature processing, its excellent interface with thermal SiO2, its higher reliability than Al gate materials, and its ability to be deposited conformally over steep topography. The shrinkage of devices below 100 nm requires more stringent and new CMP processes including poly silicon CMP. Poly silicon can be polished easily with similar pads and slurries as they are used for the planarization of silicon oxide. In this study, single crystal and poly silicon Wafers were polished as a function of pH in silica based slurry to understand and compare the polishing mechanism of silicon. The static and dynamic etch rates and removal rate were measured as a function of slurry pH (11 ~ 13). The friction force and polishing temperature were also measured at different pHs. The single crystal silicon (Bare silicon) showed higher removal rate than the poly silicon. However, higher friction force was measured on poly silicon Wafer than on Bare Wafer.
Vignesh Sundar - One of the best experts on this subject based on the ideXlab platform.
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Bare Wafer analysis for wet cleaning efficiency the impact of classification and sensitivity
Advanced Semiconductor Manufacturing Conference, 2018Co-Authors: Kay Wendt, Fabian Wilbers, Jochen Ruth, Christophe Lorant, Frank Holsteyns, John Newby, Gerhard Bast, Vignesh SundarAbstract:The continued drive in the semiconductor industry for smaller, faster and cheaper integrated circuits has driven the industry to the 10nm technology node and beyond and ushered in a new era of high-performance 3-dimensional transistor structures. Consequently, the surface preparation is becoming more challenging especially particulate contamination will continue to be a concern at increasingly demanding levels. The Maly equation, with its use of a Poisson distribution, continues to be used to predict the allowable defect density of front surface particles based on yield (targeting 99.9%) for a specific "killer defect" size, i.e. the critical particle diameter for a specific technology node, which is now less than the MPU physical gate length. This results in equipment particle specifications and provides a more tangible Roadmap1. For cleaning processes, it is not only useful to determine how well the process is removing particulate contamination but also on how many defects are being introduced during this particular cleaning step. This insight is required to get a state on the cleanliness of the process and the related tool. For this calculation, a general pre and post defect difference of the processed Wafer isn't any longer sufficient, but an improved personalized defect classification is mandatory. For example, during the pre process particle inspection scan of the Wafer, it is required to track the individual position of each defect and to classify each of them as ‘cleanable’ or ‘non-cleanable’. When performing the post process particle inspection scan, this tracking will allow determining how many ‘cleanable’ defects could be removed during a wet cleaning process and will result in the ‘cleaning efficiency’ (CE) of a particular process executed on a particular tool. Furthermore, by considering the added defects as process induced defects (PID) the cleanliness of the process/tool can be determined.
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Bare Wafer analysis for wet cleaning efficiency — The impact of classification and sensitivity
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2018Co-Authors: Kay Wendt, Fabian Wilbers, Jochen Ruth, Christophe Lorant, Frank Holsteyns, John Newby, Gerhard Bast, Vignesh SundarAbstract:The continued drive in the semiconductor industry for smaller, faster and cheaper integrated circuits has driven the industry to the 10nm technology node and beyond and ushered in a new era of high-performance 3-dimensional transistor structures. Consequently, the surface preparation is becoming more challenging especially particulate contamination will continue to be a concern at increasingly demanding levels. The Maly equation, with its use of a Poisson distribution, continues to be used to predict the allowable defect density of front surface particles based on yield (targeting 99.9%) for a specific "killer defect" size, i.e. the critical particle diameter for a specific technology node, which is now less than the MPU physical gate length. This results in equipment particle specifications and provides a more tangible Roadmap. For cleaning processes, it is not only useful to determine how well the process is removing particulate contamination but also on how many defects are being introduced during this particular cleaning step. This insight is required to get a state on the cleanliness of the process and the related tool. For this calculation, a general pre and post defect difference of the processed Wafer isn't any longer sufficient, but an improved personalized defect classification is mandatory. For example, during the pre process particle inspection scan of the Wafer, it is required to track the individual position of each defect and to classify each of them as `cleanable' or `non-cleanable'. When performing the post process particle inspection scan, this tracking will allow determining how many `cleanable' defects could be removed during a wet cleaning process and will result in the `cleaning efficiency' (CE) of a particular process executed on a particular tool. Furthermore, by considering the added defects as process induced defects (PID) the cleanliness of the process/tool can be determined.
Gerhard Bast - One of the best experts on this subject based on the ideXlab platform.
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Bare Wafer analysis for wet cleaning efficiency the impact of classification and sensitivity
Advanced Semiconductor Manufacturing Conference, 2018Co-Authors: Kay Wendt, Fabian Wilbers, Jochen Ruth, Christophe Lorant, Frank Holsteyns, John Newby, Gerhard Bast, Vignesh SundarAbstract:The continued drive in the semiconductor industry for smaller, faster and cheaper integrated circuits has driven the industry to the 10nm technology node and beyond and ushered in a new era of high-performance 3-dimensional transistor structures. Consequently, the surface preparation is becoming more challenging especially particulate contamination will continue to be a concern at increasingly demanding levels. The Maly equation, with its use of a Poisson distribution, continues to be used to predict the allowable defect density of front surface particles based on yield (targeting 99.9%) for a specific "killer defect" size, i.e. the critical particle diameter for a specific technology node, which is now less than the MPU physical gate length. This results in equipment particle specifications and provides a more tangible Roadmap1. For cleaning processes, it is not only useful to determine how well the process is removing particulate contamination but also on how many defects are being introduced during this particular cleaning step. This insight is required to get a state on the cleanliness of the process and the related tool. For this calculation, a general pre and post defect difference of the processed Wafer isn't any longer sufficient, but an improved personalized defect classification is mandatory. For example, during the pre process particle inspection scan of the Wafer, it is required to track the individual position of each defect and to classify each of them as ‘cleanable’ or ‘non-cleanable’. When performing the post process particle inspection scan, this tracking will allow determining how many ‘cleanable’ defects could be removed during a wet cleaning process and will result in the ‘cleaning efficiency’ (CE) of a particular process executed on a particular tool. Furthermore, by considering the added defects as process induced defects (PID) the cleanliness of the process/tool can be determined.
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Bare Wafer analysis for wet cleaning efficiency — The impact of classification and sensitivity
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2018Co-Authors: Kay Wendt, Fabian Wilbers, Jochen Ruth, Christophe Lorant, Frank Holsteyns, John Newby, Gerhard Bast, Vignesh SundarAbstract:The continued drive in the semiconductor industry for smaller, faster and cheaper integrated circuits has driven the industry to the 10nm technology node and beyond and ushered in a new era of high-performance 3-dimensional transistor structures. Consequently, the surface preparation is becoming more challenging especially particulate contamination will continue to be a concern at increasingly demanding levels. The Maly equation, with its use of a Poisson distribution, continues to be used to predict the allowable defect density of front surface particles based on yield (targeting 99.9%) for a specific "killer defect" size, i.e. the critical particle diameter for a specific technology node, which is now less than the MPU physical gate length. This results in equipment particle specifications and provides a more tangible Roadmap. For cleaning processes, it is not only useful to determine how well the process is removing particulate contamination but also on how many defects are being introduced during this particular cleaning step. This insight is required to get a state on the cleanliness of the process and the related tool. For this calculation, a general pre and post defect difference of the processed Wafer isn't any longer sufficient, but an improved personalized defect classification is mandatory. For example, during the pre process particle inspection scan of the Wafer, it is required to track the individual position of each defect and to classify each of them as `cleanable' or `non-cleanable'. When performing the post process particle inspection scan, this tracking will allow determining how many `cleanable' defects could be removed during a wet cleaning process and will result in the `cleaning efficiency' (CE) of a particular process executed on a particular tool. Furthermore, by considering the added defects as process induced defects (PID) the cleanliness of the process/tool can be determined.
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Progress on background signal analysis of Bare Wafer inspection systems based on light scattering for III/V epitaxial growth monitoring
25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014), 2014Co-Authors: Sandip Halder, Gerhard Bast, Yves Mols, Dieter Van Den Heuvel, Jan Van Puymbroeck, Matty Caymax, Eric Vancoille, Nancy Nieuborg, Gavin Simpson, Milko PeikertAbstract:The purpose of this paper is to elucidate other applications where the low frequency component of background signal (haze) level of a Wafer inspection tool can be used to qualitatively analyze different processes. During initial epitaxial development cycles a fast method of qualifying the growth runs is required. While SEM inspections can sub-sample the Wafer, a semi-quantitative way of qualifying growth can be immensely helpful in speeding up the process. In this paper we monitor the epitaxial growth of III/V materials by two different methods: 1) strain relaxed buffers (SRB approach); and, 2) selective epitaxial growth (SEG approach) by using the haze.
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progress on background signal analysis of Bare Wafer inspection systems based on light scattering for iii v epitaxial growth monitoring
Advanced Semiconductor Manufacturing Conference, 2014Co-Authors: Sandip Halder, Gerhard Bast, Yves Mols, Dieter Van Den Heuvel, Jan Van Puymbroeck, Matty Caymax, Eric Vancoille, Nancy Nieuborg, Gavin Simpson, Milko PeikertAbstract:The purpose of this paper is to elucidate other applications where the low frequency component of background signal (haze) level of a Wafer inspection tool can be used to qualitatively analyze different processes. During initial epitaxial development cycles a fast method of qualifying the growth runs is required. While SEM inspections can sub-sample the Wafer, a semi-quantitative way of qualifying growth can be immensely helpful in speeding up the process. In this paper we monitor the epitaxial growth of III/V materials by two different methods: 1) strain relaxed buffers (SRB approach); and, 2) selective epitaxial growth (SEG approach) by using the haze.
