The Experts below are selected from a list of 96 Experts worldwide ranked by ideXlab platform
Sudhakar Pamarti - One of the best experts on this subject based on the ideXlab platform.
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design and analysis of a programmable receiver front end with time interleaved Baseband Analog fir filtering
IEEE Journal of Solid-state Circuits, 2018Co-Authors: Sameed Hameed, Sudhakar PamartiAbstract:This paper presents time interleaving as an approach to improve the performance of programmable receiver front ends based on filtering-by-aliasing. Using two parallel periodically time-varying paths, a sharp programmable filtering response is produced at RF, while achieving a good wideband $S_{11}$ . The implemented receiver achieved a filter stopband suppression of 70 dB with a transition band of only 4 $\times$ RF bandwidth, while $S_{11}$ is better than −10 dB throughout most of the receiver local oscillator range. Analysis for achieved $S_{11}$ and noise figure are shown, while detailing methods to improve filtering performance in the presence of important circuit parasitics. The effects of mismatches between time-interleaved paths are also analyzed and quantified.
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errata for design and analysis of a programmable receiver front end based on Baseband Analog fir filtering using an lptv resistor jun 18 1592 1606
IEEE Journal of Solid-state Circuits, 2018Co-Authors: Sameed Hameed, Sudhakar PamartiAbstract:A few errors were made in the above-named work that were missed during the final production phase of the paper. While the authors made IEEE aware of these errors prior to final publication, they were unfortunately left uncorrected. The errors are corrected as follows.
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errata for design and analysis of a programmable receiver front end based on Baseband Analog fir filtering using an lptv resistor
IEEE Journal of Solid-state Circuits, 2018Co-Authors: Sameed Hameed, Sudhakar PamartiAbstract:This paper presents a programmable receiver front-end that uses periodically time-varying components. A sharp programmable filtering response was achieved at RF using a linear periodically time-varying (LPTV) resistor in conjunction with a passive mixer and an integrate-and-dump circuit. The LPTV resistor along with the integrate-and-dump circuit is shown to achieve a programmable finite-impulse response (FIR) Baseband filter. The Baseband filter is then upconverted with the passive mixer to achieve sharp bandpass filtering at the desired RF center frequency. Further, it is shown that an additional $S_{11}$ constraint can be imposed on the FIR filter design to allow for impedance matching to the antenna impedance. The implemented receiver achieved high close-in linearity with >17 dBm of IIP3 at only 1.2 $\times $ bandwidth frequency offset, while achieving a wideband impedance match with $S_{11}$ better than −10 dB throughout the local oscillator range of 0.1–1 GHz.
Kwyro Lee - One of the best experts on this subject based on the ideXlab platform.
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design methodology of Baseband Analog chain to maximize a spurious free dynamic range for atsc terrestrial and cable digital tv tuner
IEEE Transactions on Consumer Electronics, 2008Co-Authors: Kuduck Kwon, Hongteuk Kim, Kwyro LeeAbstract:This paper presents a fully integrated tunable CMOS Baseband Analog (BBA) chain optimized for advanced television systems committee (ATSC) terrestrial and cable digital TV tuner integrated circuits (ICs). To maximize the spurious free dynamic range (SFDR) of the BBA chain for both standards, the design guideline is introduced with respect to the optimized allocation of the gain of each block. The bandwidth is selectable from 3 MHz, 3.5 MHz, or 4 MHz. Fabricated in a 0.18-mum CMOS process, it provides a minimum input referred noise density of 15.5 nV/radic(Hz) with 62 dB gain and out-of-channel output referred third-order intercept point (OIP3) of 33 dBm, while it drains an average current of 89 mA from 3.3 V. The total chip area is 1 mm times 1.2 mm.
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a 2 4 ghz low power low if receiver and direct conversion transmitter in 0 18 mu hbox m cmos for ieee 802 15 4 wpan applications
IEEE Transactions on Microwave Theory and Techniques, 2007Co-Authors: Ilku Nam, Kuduck Kwon, Kyudon Choi, Joonhee Lee, Hyoukkyu Cha, Boik Seo, Kwyro LeeAbstract:In this paper, a low-power low-IF receiver and a direct-conversion transmitter (DCT) suitable for the IEEE standard 802.15.4 radio system at the 2.4-GHz band are presented in 0.18-mum deep n-well CMOS technology. By using vertical NPN (V-NPN) bipolar junction transistors in the Baseband Analog circuits of the low-IF receiver, the image rejection performance is improved and the power consumption is reduced. In addition, by applying the V-NPN current mirrored technique in a DCT, the carrier leakage is reduced and the linearity performance is improved. The receiver has 10 dB of noise figure, -15 dBm of third-order input intercept point, and 35 dBc of image rejection. The transmitter has more than -2 dBm of transmit output power, -35 dBc of local oscillator leakage, and -46 dBc of the transmit third harmonic component. The receiver and transmitter dissipate 6 and 9 mA from a 1.8-V supply, respectively
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high performance rf mixer and operational amplifier bicmos circuits using parasitic vertical bipolar transistor in cmos technology
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Ilku Nam, Kwyro LeeAbstract:The electrical characteristics of the parasitic vertical NPN (V-NPN) BJT available in deep n-well 0.18-/spl mu/m CMOS technology are presented. It has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of Early voltage, about 2 GHz of cutoff frequency, and about 4 GHz of maximum oscillation frequency at room temperature. The corner frequency of 1/f noise is lower than 4 kHz at 0.5 mA of collector current. The double-balanced RF mixer using V-NPN shows almost free 1/f noise as well as an order of magnitude smaller dc offset compared with CMOS circuit and 12 dB flat gain almost up to the cutoff frequency. The V-NPN operational amplifier for Baseband Analog circuits has higher voltage gain and better input noise and input offset performance than the CMOS ones at the identical current. These circuits using V-NPN provide the possibility of high-performance direct conversion receiver implementation in CMOS technology.
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an integrated low power cmos Baseband Analog design for direct conversion receiver
European Solid-State Circuits Conference, 2004Co-Authors: Minkyung Lee, Ickjin Kwon, Kwyro LeeAbstract:A low power CMOS receiver Baseband Analog (BBA) circuit, based on alternating filter and gain stages, is reported. For the given specifications of the Baseband Analog block, optimum allocation of the gain, IIP3 and NF of each block was performed to minimize current consumption. The fully integrated receiver BBA strip is fabricated in 0.18 /spl mu/m CMOS technology and an IIP3 of 30 dBm with a gain of 55 dB and noise figure of 31 dB are obtained at 4.86 mW power consumption.
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optimization of low power cmos Baseband Analog filter amplifier chain for direct conversion receiver
Journal of Semiconductor Technology and Science, 2004Co-Authors: Minkyung Lee, Ickjin Kwon, Kwyro LeeAbstract:A low power CMOS receiver Baseband Analog circuit based on alternating filter and gain stages reported. For the given specifications of the Baseband Analog block, optimum allocation of the gain, IIP3 and NF of the each block was performed to minimize current consumption. The fully integrated receiver BBA chain is fabricated in 0.18 I'm CMOS technolog} and IIP3 of 30 dBm with a gain of 55 dB and noise figure of 31 dB are obtained at 4.86 mW power consumption.
Sameed Hameed - One of the best experts on this subject based on the ideXlab platform.
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design and analysis of a programmable receiver front end with time interleaved Baseband Analog fir filtering
IEEE Journal of Solid-state Circuits, 2018Co-Authors: Sameed Hameed, Sudhakar PamartiAbstract:This paper presents time interleaving as an approach to improve the performance of programmable receiver front ends based on filtering-by-aliasing. Using two parallel periodically time-varying paths, a sharp programmable filtering response is produced at RF, while achieving a good wideband $S_{11}$ . The implemented receiver achieved a filter stopband suppression of 70 dB with a transition band of only 4 $\times$ RF bandwidth, while $S_{11}$ is better than −10 dB throughout most of the receiver local oscillator range. Analysis for achieved $S_{11}$ and noise figure are shown, while detailing methods to improve filtering performance in the presence of important circuit parasitics. The effects of mismatches between time-interleaved paths are also analyzed and quantified.
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errata for design and analysis of a programmable receiver front end based on Baseband Analog fir filtering using an lptv resistor jun 18 1592 1606
IEEE Journal of Solid-state Circuits, 2018Co-Authors: Sameed Hameed, Sudhakar PamartiAbstract:A few errors were made in the above-named work that were missed during the final production phase of the paper. While the authors made IEEE aware of these errors prior to final publication, they were unfortunately left uncorrected. The errors are corrected as follows.
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errata for design and analysis of a programmable receiver front end based on Baseband Analog fir filtering using an lptv resistor
IEEE Journal of Solid-state Circuits, 2018Co-Authors: Sameed Hameed, Sudhakar PamartiAbstract:This paper presents a programmable receiver front-end that uses periodically time-varying components. A sharp programmable filtering response was achieved at RF using a linear periodically time-varying (LPTV) resistor in conjunction with a passive mixer and an integrate-and-dump circuit. The LPTV resistor along with the integrate-and-dump circuit is shown to achieve a programmable finite-impulse response (FIR) Baseband filter. The Baseband filter is then upconverted with the passive mixer to achieve sharp bandpass filtering at the desired RF center frequency. Further, it is shown that an additional $S_{11}$ constraint can be imposed on the FIR filter design to allow for impedance matching to the antenna impedance. The implemented receiver achieved high close-in linearity with >17 dBm of IIP3 at only 1.2 $\times $ bandwidth frequency offset, while achieving a wideband impedance match with $S_{11}$ better than −10 dB throughout the local oscillator range of 0.1–1 GHz.
Bram Nauta - One of the best experts on this subject based on the ideXlab platform.
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2 4 ghz highly selective iot receiver front end with power optimized lnta frequency divider and Baseband Analog fir filter
IEEE Journal of Solid-state Circuits, 2021Co-Authors: Bart J Thijssen, Eric A M Klumperink, Philip Quinlan, Bram NautaAbstract:High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2 $\times $ compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal–oxide–semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An Analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm2. It consumes 370 $\mu \text{W}$ from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has −7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a −22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.
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2 4 ghz highly selective iot receiver front end with power optimized lnta frequency divider and Baseband Analog fir filter
IEEE Journal of Solid-state Circuits, 2020Co-Authors: Bart J Thijssen, Eric A M Klumperink, Philip Quinlan, Bram NautaAbstract:High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2x compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal-oxide-semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An Analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm². It consumes 370 μW from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has -7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a -22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.
R W Brodersen - One of the best experts on this subject based on the ideXlab platform.
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a 1 gb s mixed signal Baseband Analog front end for a 60 ghz wireless receiver
Symposium on VLSI Circuits, 2009Co-Authors: D A Sobel, R W BrodersenAbstract:Alow-power mixed-signal Baseband Analog front-end for 60 GHz, 1 Gb/s wireless communications has been implemented in a standard 90 nm CMOS process. The receiver is capable of operating under indoor multipath scenarios, resolving channels with up to 32 ns multipath delay spread. It uses mixed-signal equalization and carrier recovery in order to minimize the dynamic range requirements of the Analog-to-digital converter circuitry. A new mixed-signal carrier phase recovery architecture, utilizing a replica tuning scheme employing Gilbert quad variable-gain amplifiers is introduced. The Analog-to-digital converters use an active averaging technique that decouples the preamplifier gain from the averager input range, enabling enhanced suppression of mismatch-induced nonlinearities. These techniques enable a front-end with 6-bit linearity and dynamic range, while dissipating a low power consumption of 55 mW.
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a 1gbps mixed signal Analog front end for a 60ghz wireless receiver
Symposium on VLSI Circuits, 2008Co-Authors: D A Sobel, R W BrodersenAbstract:A low-power, mixed-signal, Baseband Analog front end for 60 GHz 1 Gb/s wireless communications has been implemented in a standard 90 nm CMOS process. The receiver is capable of operating under indoor multipath scenarios, resolving channels with up to 32 ns multipath delay spread. It uses mixed-signal equalization and carrier recovery in order to minimize the dynamic range requirements of the converter circuitry, resulting in a low power consumption of 55 mW.