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Baseline Profile

The Experts below are selected from a list of 1800 Experts worldwide ranked by ideXlab platform

Liang-gee Chen – 1st expert on this subject based on the ideXlab platform

  • algorithm and architecture design of power oriented h 264 avc Baseline Profile encoder for portable devices
    IEEE Transactions on Circuits and Systems for Video Technology, 2009
    Co-Authors: Yu-han Chen, Chuan-yung Tsai, Tung-chien Chen, Sung-fang Tsai, Liang-gee Chen

    Abstract:

    Because video services are becoming popular on portable devices, power becomes the primary design issue for video coders nowadays. H.264/AVC is an emerging video coding standard which can provide outstanding coding performance and thus is suitable for mobile applications. In this paper, we target a power-efficient H.264/AVC encoder. The main power consumption in an H.264/AVC encoding system is induced by data access of motion estimation (ME). At first, we propose hardware-oriented algorithms and corresponding parallel architectures of integer ME (IME) and fractional ME (FME) to achieve memory access power reduction. Then, a parameterized encoding system and flexible system architecture are proposed to provide power scalability and hardware efficiency, respectively. Finally, our design is implemented under TSMC 0.18 mum CMOS technology with 12.84 mm2 core area. The required hardware resources are 452.8 K logic gates and 16.95 KB SRAMs. The power consumption ranges from 67.2 to 43.5 mW under D1 (720 x 480) 30 frames/s video encoding, and more than 128 operating configurations are provided.

  • Algorithm and Architecture Design of Power-Oriented H.264/AVC Baseline Profile Encoder for Portable Devices
    IEEE Transactions on Circuits and Systems for Video Technology, 2009
    Co-Authors: Yu-han Chen, Chuan-yung Tsai, Tung-chien Chen, Sung-fang Tsai, Liang-gee Chen

    Abstract:

    Because video services are becoming popular on portable devices, power becomes the primary design issue for video coders nowadays. H.264/AVC is an emerging video coding standard which can provide outstanding coding performance and thus is suitable for mobile applications. In this paper, we target a power-efficient H.264/AVC encoder. The main power consumption in an H.264/AVC encoding system is induced by data access of motion estimation (ME). At first, we propose hardware-oriented algorithms and corresponding parallel architectures of integer ME (IME) and fractional ME (FME) to achieve memory access power reduction. Then, a parameterized encoding system and flexible system architecture are proposed to provide power scalability and hardware efficiency, respectively. Finally, our design is implemented under TSMC 0.18 mum CMOS technology with 12.84 mm2 core area. The required hardware resources are 452.8 K logic gates and 16.95 KB SRAMs. The power consumption ranges from 67.2 to 43.5 mW under D1 (720 x 480) 30 frames/s video encoding, and more than 128 operating configurations are provided.

  • Low Power Entropy Coding Hardware Design for H.264/AVC Baseline Profile Encoder
    2006 IEEE International Conference on Multimedia and Expo, 2006
    Co-Authors: Chuan-yung Tsai, Tung-chien Chen, Liang-gee Chen

    Abstract:

    Low power hardware design for entropy coding of H.264/AVC Baseline Profile encoder is urgent for the increasing mobile applications. However, previous works are poor in the power performance. In this paper, the first low power context-based adaptive variable length coding (CAVLC) scheme named the side information aided (SIA) symbol look ahead (SLA) one-pass CAVLC is proposed, with the non-zero and abs-one SIA flags. A reconfigurable architecture for the SLA module is also proposed to support the low power CAVLC scheme efficiently. The resultant hardware power is reduced by 69% to only 3.7 mW at 27 MHz and 1.8 V for CIF-sized video coding. The total logic gate count is 27 K gates

Chuan-yung Tsai – 2nd expert on this subject based on the ideXlab platform

  • algorithm and architecture design of power oriented h 264 avc Baseline Profile encoder for portable devices
    IEEE Transactions on Circuits and Systems for Video Technology, 2009
    Co-Authors: Yu-han Chen, Chuan-yung Tsai, Tung-chien Chen, Sung-fang Tsai, Liang-gee Chen

    Abstract:

    Because video services are becoming popular on portable devices, power becomes the primary design issue for video coders nowadays. H.264/AVC is an emerging video coding standard which can provide outstanding coding performance and thus is suitable for mobile applications. In this paper, we target a power-efficient H.264/AVC encoder. The main power consumption in an H.264/AVC encoding system is induced by data access of motion estimation (ME). At first, we propose hardware-oriented algorithms and corresponding parallel architectures of integer ME (IME) and fractional ME (FME) to achieve memory access power reduction. Then, a parameterized encoding system and flexible system architecture are proposed to provide power scalability and hardware efficiency, respectively. Finally, our design is implemented under TSMC 0.18 mum CMOS technology with 12.84 mm2 core area. The required hardware resources are 452.8 K logic gates and 16.95 KB SRAMs. The power consumption ranges from 67.2 to 43.5 mW under D1 (720 x 480) 30 frames/s video encoding, and more than 128 operating configurations are provided.

  • Algorithm and Architecture Design of Power-Oriented H.264/AVC Baseline Profile Encoder for Portable Devices
    IEEE Transactions on Circuits and Systems for Video Technology, 2009
    Co-Authors: Yu-han Chen, Chuan-yung Tsai, Tung-chien Chen, Sung-fang Tsai, Liang-gee Chen

    Abstract:

    Because video services are becoming popular on portable devices, power becomes the primary design issue for video coders nowadays. H.264/AVC is an emerging video coding standard which can provide outstanding coding performance and thus is suitable for mobile applications. In this paper, we target a power-efficient H.264/AVC encoder. The main power consumption in an H.264/AVC encoding system is induced by data access of motion estimation (ME). At first, we propose hardware-oriented algorithms and corresponding parallel architectures of integer ME (IME) and fractional ME (FME) to achieve memory access power reduction. Then, a parameterized encoding system and flexible system architecture are proposed to provide power scalability and hardware efficiency, respectively. Finally, our design is implemented under TSMC 0.18 mum CMOS technology with 12.84 mm2 core area. The required hardware resources are 452.8 K logic gates and 16.95 KB SRAMs. The power consumption ranges from 67.2 to 43.5 mW under D1 (720 x 480) 30 frames/s video encoding, and more than 128 operating configurations are provided.

  • Low Power Entropy Coding Hardware Design for H.264/AVC Baseline Profile Encoder
    2006 IEEE International Conference on Multimedia and Expo, 2006
    Co-Authors: Chuan-yung Tsai, Tung-chien Chen, Liang-gee Chen

    Abstract:

    Low power hardware design for entropy coding of H.264/AVC Baseline Profile encoder is urgent for the increasing mobile applications. However, previous works are poor in the power performance. In this paper, the first low power context-based adaptive variable length coding (CAVLC) scheme named the side information aided (SIA) symbol look ahead (SLA) one-pass CAVLC is proposed, with the non-zero and abs-one SIA flags. A reconfigurable architecture for the SLA module is also proposed to support the low power CAVLC scheme efficiently. The resultant hardware power is reduced by 69% to only 3.7 mW at 27 MHz and 1.8 V for CIF-sized video coding. The total logic gate count is 27 K gates

Tung-chien Chen – 3rd expert on this subject based on the ideXlab platform

  • algorithm and architecture design of power oriented h 264 avc Baseline Profile encoder for portable devices
    IEEE Transactions on Circuits and Systems for Video Technology, 2009
    Co-Authors: Yu-han Chen, Chuan-yung Tsai, Tung-chien Chen, Sung-fang Tsai, Liang-gee Chen

    Abstract:

    Because video services are becoming popular on portable devices, power becomes the primary design issue for video coders nowadays. H.264/AVC is an emerging video coding standard which can provide outstanding coding performance and thus is suitable for mobile applications. In this paper, we target a power-efficient H.264/AVC encoder. The main power consumption in an H.264/AVC encoding system is induced by data access of motion estimation (ME). At first, we propose hardware-oriented algorithms and corresponding parallel architectures of integer ME (IME) and fractional ME (FME) to achieve memory access power reduction. Then, a parameterized encoding system and flexible system architecture are proposed to provide power scalability and hardware efficiency, respectively. Finally, our design is implemented under TSMC 0.18 mum CMOS technology with 12.84 mm2 core area. The required hardware resources are 452.8 K logic gates and 16.95 KB SRAMs. The power consumption ranges from 67.2 to 43.5 mW under D1 (720 x 480) 30 frames/s video encoding, and more than 128 operating configurations are provided.

  • Algorithm and Architecture Design of Power-Oriented H.264/AVC Baseline Profile Encoder for Portable Devices
    IEEE Transactions on Circuits and Systems for Video Technology, 2009
    Co-Authors: Yu-han Chen, Chuan-yung Tsai, Tung-chien Chen, Sung-fang Tsai, Liang-gee Chen

    Abstract:

    Because video services are becoming popular on portable devices, power becomes the primary design issue for video coders nowadays. H.264/AVC is an emerging video coding standard which can provide outstanding coding performance and thus is suitable for mobile applications. In this paper, we target a power-efficient H.264/AVC encoder. The main power consumption in an H.264/AVC encoding system is induced by data access of motion estimation (ME). At first, we propose hardware-oriented algorithms and corresponding parallel architectures of integer ME (IME) and fractional ME (FME) to achieve memory access power reduction. Then, a parameterized encoding system and flexible system architecture are proposed to provide power scalability and hardware efficiency, respectively. Finally, our design is implemented under TSMC 0.18 mum CMOS technology with 12.84 mm2 core area. The required hardware resources are 452.8 K logic gates and 16.95 KB SRAMs. The power consumption ranges from 67.2 to 43.5 mW under D1 (720 x 480) 30 frames/s video encoding, and more than 128 operating configurations are provided.

  • Low Power Entropy Coding Hardware Design for H.264/AVC Baseline Profile Encoder
    2006 IEEE International Conference on Multimedia and Expo, 2006
    Co-Authors: Chuan-yung Tsai, Tung-chien Chen, Liang-gee Chen

    Abstract:

    Low power hardware design for entropy coding of H.264/AVC Baseline Profile encoder is urgent for the increasing mobile applications. However, previous works are poor in the power performance. In this paper, the first low power context-based adaptive variable length coding (CAVLC) scheme named the side information aided (SIA) symbol look ahead (SLA) one-pass CAVLC is proposed, with the non-zero and abs-one SIA flags. A reconfigurable architecture for the SLA module is also proposed to support the low power CAVLC scheme efficiently. The resultant hardware power is reduced by 69% to only 3.7 mW at 27 MHz and 1.8 V for CIF-sized video coding. The total logic gate count is 27 K gates