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Binary Equivalent

The Experts below are selected from a list of 255 Experts worldwide ranked by ideXlab platform

Seokhyeong Kang – 1st expert on this subject based on the ideXlab platform

  • Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors
    IEEE Electron Device Letters, 2018
    Co-Authors: Seokhyeong Kang

    Abstract:

    Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10-16 J, which is comparable to the Binary Equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors.

Colleen C Nelson – 2nd expert on this subject based on the ideXlab platform

  • MiRDeep*: An integrated application tool for miRNA identification from RNA sequencing data
    Nucleic Acids Research, 2013
    Co-Authors: Jiyuan An, John Lai, Melanie L. Lehman, Colleen C Nelson

    Abstract:

    miRDeep and its varieties are widely used to quantify known and novel micro RNA (miRNA) from small RNA sequencing (RNAseq). This article describes miRDeep*, our integrated miRNA identification tool, which is modeled off miRDeep, but the precision of detecting novel miRNAs is improved by introducing new strategies to identify precursor miRNAs. miRDeep* has a user-friendly graphic interface and accepts raw data in FastQ and Sequence Alignment Map (SAM) or the Binary Equivalent (BAM) format. Known and novel miRNA expression levels, as measured by the number of reads, are displayed in an interface, which shows each RNAseq read relative to the pre-miRNA hairpin. The secondary pre-miRNA structure and read locations for each predicted miRNA are shown and kept in a separate figure file. Moreover, the target genes of known and novel miRNAs are predicted using the TargetScan algorithm, and the targets are ranked according to the confidence score. miRDeep* is an integrated standalone application where sequence alignment, pre-miRNA secondary structure calculation and graphical display are purely Java coded. This application tool can be executed using a normal personal computer with 1.5 GB of memory. Further, we show that miRDeep* outperformed existing miRNA prediction tools using our LNCaP and other small RNAseq datasets. miRDeep* is freely available online at http://www.australianprostatecentre.org/research/software/mirdeep-star.

Luigi Carro – 3rd expert on this subject based on the ideXlab platform

  • VLSI-SoC – A low power high performance CMOS voltage-mode quaternary full adder
    2006 IFIP International Conference on Very Large Scale Integration, 2006
    Co-Authors: Ricardo Cunha Goncalves Da Silva, Henri Ivanov Boudinov, Luigi Carro

    Abstract:

    Multiple-valued logic, despite of all its theoretical potentialities, has not provided real advantages for arithmetic circuits when compared to the Binary Equivalent ones until now. This paper shows a new efficient method to implement quaternary logic arithmetic circuits using multi-threshold transistors, where 3 power supply lines are used to perform quaternary circuits with low power consumption and high performance. As a demonstration, a quaternary full adder is described in TSMC 0.18?m technology and compared to regular Binary circuits, presenting a 76% reduction in power consumption, and an improvement of 15% regarding speed with a 20% area overhead.

  • A low power high performance CMOS voltage-mode quaternary full adder
    2006 IFIP International Conference on Very Large Scale Integration, 2006
    Co-Authors: Ricardo Cunha Goncalves Da Silva, Henri Ivanov Boudinov, Luigi Carro

    Abstract:

    Multiple-valued logic, despite of all its theoretical potentialities, has not provided real advantages for arithmetic circuits when compared to the Binary Equivalent ones until now. This paper shows a new efficient method to implement quaternary logic arithmetic circuits using multi-threshold transistors, where 3 power supply lines are used to perform quaternary circuits with low power consumption and high performance. As a demonstration, a quaternary full adder is described in TSMC 0.18mum technology and compared to regular Binary circuits, presenting a 76% reduction in power consumption, and an improvement of 15% regarding speed with a 20% area overhead