The Experts below are selected from a list of 777555 Experts worldwide ranked by ideXlab platform

Megumi Ishiduki - One of the best experts on this subject based on the ideXlab platform.

  • Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices
    2009 Symposium on VLSI Technology, 2009
    Co-Authors: Ryota Katsumata, Yosuke Komori, Masaru Kito, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Megumi Ishiduki, Masaru Kido, Tomoko Fujiwara, Junya Matsunami, Yuzo Nagata
    Abstract:

    We propose pipe-shaped bit cost scalable (P-BiCS) flash memory which consists of pipe-shaped NAND strings folded like a u-shape instead of the straight-shape. P-BiCS flash technology achieves a highly reliable memory film of which the program and erase (P/E) operation is managed by Fowler-Nordheim (FN) tunneling, that is originated by the strong curvature effect of its small pipe radius, a low resistance source line by the layered metal wirings and a tightly controlled diffusion profile for the select-gate (SG) transistor due to low thermal budget. The effective 1-bit cell area of 0.00082 mum2 and its functionality are successfully demonstrated using the 32 Gbit test chip with the 3-dimensionally 16 stacked layers and the multi-level-cell (MLC) operation by 60 nm P-BiCS flash technology.

  • multi stacked 1g cell layer pipe shaped bics flash memory
    Symposium on VLSI Circuits, 2009
    Co-Authors: Takashi Maeda, Yosuke Komori, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Kiyotaro Itagaki, Tomoo Hishida, M Kido, Megumi Ishiduki
    Abstract:

    A three-dimensional 16 stacked 1G cell/layer Pipe-shaped Bit-Cost Scalable (P-BiCS) flash memory test chip with 60nm technology has been developed. The effective 1-bit cell size is 0.00082 um2. This paper describes the branched control gate configuration and the new erase operation which are suitable for P-BiCS flash memory. P-BiCS flash memory is one of the most promising candidates for realizing the future T-bit storage device.

  • Optimal device structure for Pipe-shaped BiCS Flash memory for ultra high density storage device with excellent performance and reliability
    2009 IEEE International Electron Devices Meeting (IEDM), 2009
    Co-Authors: Megumi Ishiduki, Yosuke Komori, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Yuzo Nagata, Masaru Kido, Tomoko Fujiwara, Takashi Maeda
    Abstract:

    An asymmetric source/drain profile for select gate and metal salicided control gate are successfully realized on Pipe-shaped Bit Cost Scalable (P-BiCS) Flash memory to achieve data storage device with excellent performance and reliability.

Gerhard Kramer - One of the best experts on this subject based on the ideXlab platform.

  • capacity of two relay diamond networks with rate limited links to the relays and a binary adder multiple access channel
    International Symposium on Information Theory, 2016
    Co-Authors: Shirin Saeedi Bidokhti, Gerhard Kramer
    Abstract:

    A class of two-relay diamond networks is studied where the broadcast component is modelled by two independent Bit-Pipes and the multiple-access component is memoryless. A new upper is derived on the capacity which generalizes bounding techniques of Ozarow for the Gaussian multiple description problem (1981) and Kang and Liu for the Gaussian diamond network (2011). For binary adder MACs, the upper bound establishes the capacity for all ranges of Bit-Pipe capacities.

  • Capacity Bounds for Diamond Networks With an Orthogonal Broadcast Channel
    IEEE Transactions on Information Theory, 2016
    Co-Authors: Shirin Saeedi Bidokhti, Gerhard Kramer
    Abstract:

    A class of diamond networks is studied where the broadcast component is orthogonal and modeled by two independent Bit-Pipes. New upper and lower bounds on the capacity are derived. The proof technique for the upper bound generalizes the bounding techniques of Ozarow for the Gaussian multiple description problem (1981) and Kang and Liu for the Gaussian diamond network (2011). The lower bound is based on Marton's coding technique and superposition coding. The bounds are evaluated for Gaussian and binary adder multiple access channels (MACs). For Gaussian MACs, both the lower and upper bounds strengthen the Kang-Liu bounds and establish capacity for interesting ranges of Bit-Pipe capacities. For binary adder MACs, the capacity is established for all the ranges of Bit-Pipe capacities.

  • capacity bounds for diamond networks with an orthogonal broadcast channel
    arXiv: Information Theory, 2015
    Co-Authors: Shirin Saeedi Bidokhti, Gerhard Kramer
    Abstract:

    A class of diamond networks is studied where the broadcast component is orthogonal and modeled by two independent Bit-Pipes. New upper and lower bounds on the capacity are derived. The proof technique for the upper bound generalizes bounding techniques of Ozarow for the Gaussian multiple description problem (1981) and Kang and Liu for the Gaussian diamond network (2011). The lower bound is based on Marton's coding technique and superposition coding. The bounds are evaluated for Gaussian and binary adder multiple access channels (MACs). For Gaussian MACs, both the lower and upper bounds strengthen the Kang-Liu bounds and establish capacity for interesting ranges of Bit-Pipe capacities. For binary adder MACs, the capacity is established for all ranges of Bit-Pipe capacities.

Takashi Maeda - One of the best experts on this subject based on the ideXlab platform.

Ryota Katsumata - One of the best experts on this subject based on the ideXlab platform.

  • Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices
    2009 Symposium on VLSI Technology, 2009
    Co-Authors: Ryota Katsumata, Yosuke Komori, Masaru Kito, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Megumi Ishiduki, Masaru Kido, Tomoko Fujiwara, Junya Matsunami, Yuzo Nagata
    Abstract:

    We propose pipe-shaped bit cost scalable (P-BiCS) flash memory which consists of pipe-shaped NAND strings folded like a u-shape instead of the straight-shape. P-BiCS flash technology achieves a highly reliable memory film of which the program and erase (P/E) operation is managed by Fowler-Nordheim (FN) tunneling, that is originated by the strong curvature effect of its small pipe radius, a low resistance source line by the layered metal wirings and a tightly controlled diffusion profile for the select-gate (SG) transistor due to low thermal budget. The effective 1-bit cell area of 0.00082 mum2 and its functionality are successfully demonstrated using the 32 Gbit test chip with the 3-dimensionally 16 stacked layers and the multi-level-cell (MLC) operation by 60 nm P-BiCS flash technology.

  • multi stacked 1g cell layer pipe shaped bics flash memory
    Symposium on VLSI Circuits, 2009
    Co-Authors: Takashi Maeda, Yosuke Komori, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Kiyotaro Itagaki, Tomoo Hishida, M Kido, Megumi Ishiduki
    Abstract:

    A three-dimensional 16 stacked 1G cell/layer Pipe-shaped Bit-Cost Scalable (P-BiCS) flash memory test chip with 60nm technology has been developed. The effective 1-bit cell size is 0.00082 um2. This paper describes the branched control gate configuration and the new erase operation which are suitable for P-BiCS flash memory. P-BiCS flash memory is one of the most promising candidates for realizing the future T-bit storage device.

  • Optimal device structure for Pipe-shaped BiCS Flash memory for ultra high density storage device with excellent performance and reliability
    2009 IEEE International Electron Devices Meeting (IEDM), 2009
    Co-Authors: Megumi Ishiduki, Yosuke Komori, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Yuzo Nagata, Masaru Kido, Tomoko Fujiwara, Takashi Maeda
    Abstract:

    An asymmetric source/drain profile for select gate and metal salicided control gate are successfully realized on Pipe-shaped Bit Cost Scalable (P-BiCS) Flash memory to achieve data storage device with excellent performance and reliability.

Yoshiaki Fukuzumi - One of the best experts on this subject based on the ideXlab platform.

  • Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices
    2009 Symposium on VLSI Technology, 2009
    Co-Authors: Ryota Katsumata, Yosuke Komori, Masaru Kito, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Megumi Ishiduki, Masaru Kido, Tomoko Fujiwara, Junya Matsunami, Yuzo Nagata
    Abstract:

    We propose pipe-shaped bit cost scalable (P-BiCS) flash memory which consists of pipe-shaped NAND strings folded like a u-shape instead of the straight-shape. P-BiCS flash technology achieves a highly reliable memory film of which the program and erase (P/E) operation is managed by Fowler-Nordheim (FN) tunneling, that is originated by the strong curvature effect of its small pipe radius, a low resistance source line by the layered metal wirings and a tightly controlled diffusion profile for the select-gate (SG) transistor due to low thermal budget. The effective 1-bit cell area of 0.00082 mum2 and its functionality are successfully demonstrated using the 32 Gbit test chip with the 3-dimensionally 16 stacked layers and the multi-level-cell (MLC) operation by 60 nm P-BiCS flash technology.

  • multi stacked 1g cell layer pipe shaped bics flash memory
    Symposium on VLSI Circuits, 2009
    Co-Authors: Takashi Maeda, Yosuke Komori, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Kiyotaro Itagaki, Tomoo Hishida, M Kido, Megumi Ishiduki
    Abstract:

    A three-dimensional 16 stacked 1G cell/layer Pipe-shaped Bit-Cost Scalable (P-BiCS) flash memory test chip with 60nm technology has been developed. The effective 1-bit cell size is 0.00082 um2. This paper describes the branched control gate configuration and the new erase operation which are suitable for P-BiCS flash memory. P-BiCS flash memory is one of the most promising candidates for realizing the future T-bit storage device.

  • Optimal device structure for Pipe-shaped BiCS Flash memory for ultra high density storage device with excellent performance and reliability
    2009 IEEE International Electron Devices Meeting (IEDM), 2009
    Co-Authors: Megumi Ishiduki, Yosuke Komori, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Yuzo Nagata, Masaru Kido, Tomoko Fujiwara, Takashi Maeda
    Abstract:

    An asymmetric source/drain profile for select gate and metal salicided control gate are successfully realized on Pipe-shaped Bit Cost Scalable (P-BiCS) Flash memory to achieve data storage device with excellent performance and reliability.