The Experts below are selected from a list of 6216 Experts worldwide ranked by ideXlab platform

Chinyu Huang - One of the best experts on this subject based on the ideXlab platform.

  • a greedy based method for modified condition decision coverage testing criterion
    Symposium on Reliable Distributed Systems, 2017
    Co-Authors: Chinyu Huang
    Abstract:

    During software regression testing, the code coverage of target program is a crucial factor while we perform test case reduction and prioritization. Modified Condition/ Decision Coverage (MC/DC) is one of the most strict and high-accuracy criterion in code coverage and it is usually considered necessary for adequate testing of critical software. In the past, Hayhurst et al proposed a method to implement the MC/DC criterion that complies with regulatory guidance for DO-178B level A software. Hayhurst's MC/DC approach was to find some test cases which are satisfied by MC/DC criterion for each operator (and, or, not, or xor) in the Boolean Expression. However, there could be some problems when using Hayhurst's MC/DC approach to select test cases. In this paper, we discuss how to improve and/or enhance Hayhurst's MC/DC approach by using a greedy-based method. Some experiments are performed based on real programs to evaluate as well as compare the performance of our proposed and Hayhurst's approaches.

  • a study of enhanced mc dc coverage criterion for software testing
    Computer Software and Applications Conference, 2007
    Co-Authors: Junru Chang, Chinyu Huang
    Abstract:

    The coverage criteria of verification techniques play an important role in software development and testing. The goal is to reduce the size of test suites to economize on time, and to ensure whether all statements (or conditions) are covered. We can use these criteria to track test progress, assess current situations, predict emerging events, and so on. Thus we can take the necessary actions upon early indications that testing activity is falling behind. Modified condition/decision coverage (MC/DC) was proposed by NASA in 1994, and had been widely adopted and discussed since then. As evident from the definition, MC/DC criterion is used to judge whether each Boolean operator can be satisfied or not. However, we find that the selected test cases sometimes may not be able to satisfy the original definition of MC/DC under some Boolean Expressions. In this paper, we will propose a simple but useful method which focuses on all conditions of Boolean Expression to practice MC/DC. Specifically, our proposed approach will use n-cube graph and Gray code to implement the MC/DC criterion. We will further show how to use the proposed method to differentiate the necessary and redundancy test cases. Finally, a practical regression testing tool, TASTE (Tool for Automatic Software regression TEsting), will be presented in this paper. An example is given to illustrate the detailed working process and is explained in detail.

Angelo Gargantini - One of the best experts on this subject based on the ideXlab platform.

  • optimal test suite generation for modified condition decision coverage using sat solving
    International Conference on Computer Safety Reliability and Security, 2018
    Co-Authors: Takashi Kitamura, Quentin Maissonneuve, Eunhye Choi, Cyrille Artho, Angelo Gargantini
    Abstract:

    Boolean Expressions occur frequently in descriptions of computer systems, but they tend to be complex and error-prone in complex systems. The modified condition decision coverage (MCDC) criterion in system testing is an important testing technique for Boolean Expression, as its usage mandated by safety standards such as DO-178 [1] (avionics) and ISO26262 [2] (automotive). In this paper, we develop an algorithm to generate optimal MCDC test suites for Boolean Expressions. Our algorithm is based on SAT solving and generates minimal MCDC test suites. Experiments on a real-world avionics system confirm that the technique can construct minimal MCDC test suites within reasonable times, and improves significantly upon prior techniques.

  • dealing with constraints in Boolean Expression testing
    International Conference on Software Testing Verification and Validation Workshops, 2011
    Co-Authors: Angelo Gargantini
    Abstract:

    When testing a Boolean Expression, one should consider also the constraints among the variables contained in it. Constraints model interdependence among the conditions in the Expressions. Only tests that satisfy the constraints. i.e. valid tests, are really useful and can be applied to test the Expression. We present three ways to deal with such constraints: (1) ignoring them during test generation and removing invalid tests later, (2) including them in the Expression as conjoint and again removing invalid tests later, and (3) considering them during the test generation process in order to generate only valid tests from the start. We introduce a general framework in which the three policies are implemented and compared over a set of Boolean Expressions commonly used as benchmarks. Although the third policy requires a constraints solving technique for actual test generation, it presents several benefits: it generates smaller test suites and it may require less time for tests generation. Moreover, ignoring the constraints during test generation can reduce the fault detection capability of the tests.

Eungi Kim - One of the best experts on this subject based on the ideXlab platform.

  • Derivations of Single Hypothetical Don't-Care Minterms Using the Quasi Quine-McCluskey Method
    2016
    Co-Authors: Eungi Kim
    Abstract:

    Abstract Automatically deriving only individual don't-care minterms that can effectively reduce a Boolean logic Expressions are being investigated. Don't-care conditions play an important role in optimizing logic design. The type of unknown don't-care minterms that can always reduce the number of product terms in Boolean Expression are referred as single hypothetical don't-care (S-HDC) minterms. This paper describes the Quasi Quine-McCluskey method that systematically derives S-HDC minterms. For the most part, this method is similar to the original Quine-McCluskey method in deriving the prime implicants. However, the Quasi Quine-McCluskey method further derives S-HDC minterms by applying so-called a combinatorial comparison operation. Upon completion of the procedure, the designer can review generated S-HDC minterms to test its appropriateness for a particular application. Key Words: minterm, don't-care condition, Quine-McCluskey method, Karnaugh Map 1

  • derivations of single hypothetical don t care minterms using the quasi quine mccluskey method
    Journal of the Korea Industrial Information Systems Research, 2013
    Co-Authors: Eungi Kim
    Abstract:

    Automatically deriving only individual don"t-care minterms that can effectively reduce a Boolean logic Expressions are being investigated. Don"t-care conditions play an important role in optimizing logic design. The type of unknown don"t-care minterms that can always reduce the number of product terms in Boolean Expression are referred as single hypothetical don"t-care (S-HDC) minterms. This paper describes the Quasi Quine-McCluskey method that systematically derives S-HDC minterms. For the most part, this method is similar to the original Quine-McCluskey method in deriving the prime implicants. However, the Quasi Quine-McCluskey method further derives S-HDC minterms by applying so-called a combinatorial comparison operation. Upon completion of the procedure, the designer can review generated S-HDC minterms to test its appropriateness for a particular application.

  • multi level groupings of minterms using the decimal valued matrix method
    Journal of the Korea Society of Computer and Information, 2012
    Co-Authors: Eungi Kim
    Abstract:

    This paper suggests an improved method of grouping minterms based on the Decimal-Valued Matrix (DVM) method. The DVM is a novel approach to Boolean logic minimization method which was recently developed by this author. Using the minterm-based matrix layout, the method captures binary number based minterm differences in decimal number form. As a result, combinable minterms can be visually identified. Furthermore, they can be systematically processed in finding a minimized Boolean Expression. Although this new matrix based approach is visual-based, the suggested method in symmetric grouping cell values can become rather messy in some cases. To alleviate this problem, the enhanced DVM method that is based on multi-level groupings of combinable minterms is presented in this paper. Overall, since the method described here provides a concise visualization of minterm groupings, it facilitates a user with more options to explore different combinable minterm groups for a given Boolean logic minimization problem.

Henrik Hulgaard - One of the best experts on this subject based on the ideXlab platform.

  • Satisfiability checking using Boolean Expression Diagrams
    International Journal on Software Tools for Technology Transfer, 2003
    Co-Authors: Poul F. Williams, Henrik Reif Andersen, Henrik Hulgaard
    Abstract:

    In this paper we present an algorithm for determining satisfiability of general Boolean formulas which are not necessarily in conjunctive normal form. The algorithm extends the well-known Davis–Putnam algorithm to work on Boolean formulas represented using Boolean Expression Diagrams (BEDs). The BED data structure allows the algorithm to take advantage of the built-in reduction rules and the sharing of sub-formulas. Furthermore, it is possible to combine the algorithm with traditional BDD construction (using Bryant’s Apply-procedure). By adjusting a single parameter to the BedSat algorithm, it is possible to control to what extent the algorithm behaves like the Apply-algorithm or like a SAT-solver. Thus, the algorithm can be seen as bridging the gap between standard SAT-solvers and BDDs. We present promising experimental results for 566 non-clausal formulas obtained from the multi-level combinational circuits in the ISCAS’85 benchmark suite and from performing model checking of a shift-and-add multiplier.

  • equivalence checking of combinational circuits using Boolean Expression diagrams
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999
    Co-Authors: Henrik Hulgaard, Poul F. Williams, Henrik Reif Andersen
    Abstract:

    The combinational logic-level equivalence problem is to determine whether two given combinational circuits implement the same Boolean function. This problem arises in a number of computer-aided design (CAD) applications, for example when checking the correctness of incremental design changes (performed either manually or by a design automation tool). This paper introduces a data structure called Boolean Expression diagrams (BEDs) and two algorithms for transforming a BED into a reduced ordered binary decision diagram (OBDD). BEDs are capable of representing any Boolean circuit in linear space and can exploit structural similarities between the two circuits that are compared. These properties make BEDs suitable for verifying the equivalence of combinational circuits. BEDs can be seen as an intermediate representation between circuits (which are compact) and OBDD's (which are canonical). Based on a large number of combinational circuits, we demonstrate that BEDs either outperform or achieve results comparable to both standard OBDD approaches and the techniques specifically developed to exploit structural similarities for efficiently solving the equivalence problem. Due to the simplicity and generality of BEDs, it is to be expected that combining them with other approaches to equivalence checking will be both straightforward and beneficial.

  • Boolean Expression diagrams
    Logic in Computer Science, 1997
    Co-Authors: Henrik Reif Andersen, Henrik Hulgaard
    Abstract:

    This paper presents a new data structure called Boolean Expression Diagrams (BEDs) for representing and manipulating Boolean functions. BEDs are a generalization of Binary Decision Diagrams (BDDs) which can represent any Boolean circuit in linear space and still maintain many of the desirable properties of BDDs. Two algorithms are described for transforming a BED into a reduced ordered BDD. One closely mimics the BDD apply-operator while the other can exploit the structural information of the Boolean Expression. The efficacy of the BED representation is demonstrated by verifying that the redundant and non-redundant versions of the ISCAS 85 benchmark circuits are identical. In particular, it is verified that the two 16-bit multiplication circuits (c6288 and c6288nr) implement the same Boolean functions. Using BEDs, this verification problem is solved in less than a second, while using standard BDD techniques this problem is infeasible. BEDs are useful in applications where the end-result as a reduced ordered BDD is small, for example for tautology checking.

  • Boolean Expression diagrams extended abstract
    Logic in Computer Science, 1997
    Co-Authors: Henrik Reif Andersen, Henrik Hulgaard
    Abstract:

    This paper presents a new data structure called Boolean Expression Diagrams (BEDs) for representing and manipulating Boolean functions. BEDs are a generalization of Binary Decision Diagrams (BDDs) which can represent any Boolean circuit in linear space and still maintain many of the desirable properties of BDDs. Two algorithms are described for transforming a BED into a reduced ordered BDD. One closely mimics the BDD apply-operator while the other can exploit the structural information of the Boolean Expression. The eficacy of the BED representation is demonstrated by verifying that the redundant and non-redundant versions of the ISCAS 85 benchmark circuits are identical. In particular, it is verified that the two 16-bit multiplication circuits (c6288 and c6288nr) implement the same Boolean functions. Using BEDs, this verification problem is solved in less than a second, while using standard BDD techniques this problem is infeasible. BEDs are useful in applications where the end-result as a reduced ordered BDD is small, for example for tautology checking.

Antoine Rauzy - One of the best experts on this subject based on the ideXlab platform.

  • model synthesis using Boolean Expression diagrams
    Reliability Engineering & System Safety, 2019
    Co-Authors: Liu Yang, Antoine Rauzy
    Abstract:

    Abstract In this article, we propose a new method for fault tree analysis, called model synthesis, which comes in addition to traditional assessment techniques. It consists in rewriting the fault tree under study, or the set of minimal cutsets extracted from this fault tree, so to make some relevant information emerge. Our implementation of model synthesis relies on encoding Boolean formulas by means of zero-suppressed Boolean Expression diagrams. Rewriting heuristics are efficiently implemented by means of local operations on these diagrams. A key feature of zero-suppressed Boolean Expression diagrams is that they make it possible to perform partial normalization of Boolean formulas, avoiding in this way the exponential blow-up of calculation resources most of the other methods suffer from. We show how to take advantage of the architecture of the systems under study to guide rewriting heuristics. We illustrate the principles of model synthesis and of its implementation by means of examples.