The Experts below are selected from a list of 2742 Experts worldwide ranked by ideXlab platform
Rami Melhem - One of the best experts on this subject based on the ideXlab platform.
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on the emulation of finite Buffered Output queued switches using combined input Output queuing
International Symposium on Distributed Computing, 2008Co-Authors: Mahmoud Elhaddad, Rami MelhemAbstract:We study the emulation of Output Queuing (OQ) using Combined Input-Output Queuing (CIOQ) switches in the setting where the emulated OQ switch and the CIOQ switch have buffer capacity Bi¾? 1 packets at every Output. We analyze the resource requirements of CIOQ policies in terms of the required fabric speedup and the additional buffer capacity needed at the CIOQ inputs. For the family of work-conserving scheduling algorithms, we find that whereas every greedy CIOQ policy is valid for OQ emulation at speedup B, no CIOQ policy is valid at speedup $s when preemption is allowed. We also find that CCF in particular is not valid at any speedup s< B. We then introduce a CIOQ policy, CEH, that is valid at speedup $s \geq \sqrt{2(B-1)}$. Under CEH, the buffer occupancy at any input never exceeds $1+\lfloor\frac{B-1}{s-1}\rfloor$. For non-preemptive scheduling algorithms, we characterize a trade-off between the CIOQ speedup and the input buffer occupancy. Specifically, we show that for any greedypolicy that is valid at speedup s> 2, the input buffer occupancy cannot exceed $1+\lceil{\frac{B-1}{s-2}}\rceil$. We also show that at speedup 2, a greedy variant of the CCF policy requires input buffer capacity of only Bpackets for the emulation of non-preemptive OQ algorithms with PIFO service disciplines.
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DISC - On the Emulation of Finite-Buffered Output Queued Switches Using Combined Input-Output Queuing
Lecture Notes in Computer Science, 1Co-Authors: Mahmoud Elhaddad, Rami MelhemAbstract:We study the emulation of Output Queuing (OQ) using Combined Input-Output Queuing (CIOQ) switches in the setting where the emulated OQ switch and the CIOQ switch have buffer capacity Bi¾? 1 packets at every Output. We analyze the resource requirements of CIOQ policies in terms of the required fabric speedup and the additional buffer capacity needed at the CIOQ inputs. For the family of work-conserving scheduling algorithms, we find that whereas every greedy CIOQ policy is valid for OQ emulation at speedup B, no CIOQ policy is valid at speedup $s when preemption is allowed. We also find that CCF in particular is not valid at any speedup s< B. We then introduce a CIOQ policy, CEH, that is valid at speedup $s \geq \sqrt{2(B-1)}$. Under CEH, the buffer occupancy at any input never exceeds $1+\lfloor\frac{B-1}{s-1}\rfloor$. For non-preemptive scheduling algorithms, we characterize a trade-off between the CIOQ speedup and the input buffer occupancy. Specifically, we show that for any greedypolicy that is valid at speedup s> 2, the input buffer occupancy cannot exceed $1+\lceil{\frac{B-1}{s-2}}\rceil$. We also show that at speedup 2, a greedy variant of the CCF policy requires input buffer capacity of only Bpackets for the emulation of non-preemptive OQ algorithms with PIFO service disciplines.
Mahmoud Elhaddad - One of the best experts on this subject based on the ideXlab platform.
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on the emulation of finite Buffered Output queued switches using combined input Output queuing
International Symposium on Distributed Computing, 2008Co-Authors: Mahmoud Elhaddad, Rami MelhemAbstract:We study the emulation of Output Queuing (OQ) using Combined Input-Output Queuing (CIOQ) switches in the setting where the emulated OQ switch and the CIOQ switch have buffer capacity Bi¾? 1 packets at every Output. We analyze the resource requirements of CIOQ policies in terms of the required fabric speedup and the additional buffer capacity needed at the CIOQ inputs. For the family of work-conserving scheduling algorithms, we find that whereas every greedy CIOQ policy is valid for OQ emulation at speedup B, no CIOQ policy is valid at speedup $s when preemption is allowed. We also find that CCF in particular is not valid at any speedup s< B. We then introduce a CIOQ policy, CEH, that is valid at speedup $s \geq \sqrt{2(B-1)}$. Under CEH, the buffer occupancy at any input never exceeds $1+\lfloor\frac{B-1}{s-1}\rfloor$. For non-preemptive scheduling algorithms, we characterize a trade-off between the CIOQ speedup and the input buffer occupancy. Specifically, we show that for any greedypolicy that is valid at speedup s> 2, the input buffer occupancy cannot exceed $1+\lceil{\frac{B-1}{s-2}}\rceil$. We also show that at speedup 2, a greedy variant of the CCF policy requires input buffer capacity of only Bpackets for the emulation of non-preemptive OQ algorithms with PIFO service disciplines.
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DISC - On the Emulation of Finite-Buffered Output Queued Switches Using Combined Input-Output Queuing
Lecture Notes in Computer Science, 1Co-Authors: Mahmoud Elhaddad, Rami MelhemAbstract:We study the emulation of Output Queuing (OQ) using Combined Input-Output Queuing (CIOQ) switches in the setting where the emulated OQ switch and the CIOQ switch have buffer capacity Bi¾? 1 packets at every Output. We analyze the resource requirements of CIOQ policies in terms of the required fabric speedup and the additional buffer capacity needed at the CIOQ inputs. For the family of work-conserving scheduling algorithms, we find that whereas every greedy CIOQ policy is valid for OQ emulation at speedup B, no CIOQ policy is valid at speedup $s when preemption is allowed. We also find that CCF in particular is not valid at any speedup s< B. We then introduce a CIOQ policy, CEH, that is valid at speedup $s \geq \sqrt{2(B-1)}$. Under CEH, the buffer occupancy at any input never exceeds $1+\lfloor\frac{B-1}{s-1}\rfloor$. For non-preemptive scheduling algorithms, we characterize a trade-off between the CIOQ speedup and the input buffer occupancy. Specifically, we show that for any greedypolicy that is valid at speedup s> 2, the input buffer occupancy cannot exceed $1+\lceil{\frac{B-1}{s-2}}\rceil$. We also show that at speedup 2, a greedy variant of the CCF policy requires input buffer capacity of only Bpackets for the emulation of non-preemptive OQ algorithms with PIFO service disciplines.
Sudhanshu Maheshwari - One of the best experts on this subject based on the ideXlab platform.
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Single Active Element Based Cascadable Band-Pass Filters for Low-Q Applications
Journal of Circuits Systems and Computers, 2015Co-Authors: Bhartendu Chaturvedi, Sudhanshu MaheshwariAbstract:The paper presents new single active element based second order band pass filters. The new circuits use single dual-X current conveyor with Buffered Output and five passive components. The proposed circuits enjoy the features of high input impedance and low Output impedance, which are desirable features for voltage-mode circuits. Circuit operation at high frequencies are verified along with non-ideality and parasitic study. The Monte Carlo analysis is also done which justify good sensitivity performances of the proposed circuits. Routh–Hurwitz's stability test is performed to verify the stability of the proposed circuits. For showing the integration aspect, resistorless band-pass filters are also realized. The proposed low-Q filters are useful for cascading. The feature of cascadability is further utilized by showing an application of fourth-order band-pass filter. The performances of the proposed circuits are depicted through Personal Simulation Program with Integrated Circuit Emphasis (PSPICE) simulations, which show good agreement to theoretical applications. The new circuits are expected to enhance the already existing knowledge on the subject.
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Current conveyor all-pass sections: brief review and novel solution.
TheScientificWorldJournal, 2013Co-Authors: Sudhanshu MaheshwariAbstract:This study relates to the review of an important analog electronic function in form of all-pass filter's realization using assorted current conveyor types and their relative performances, which resulted in a novel solution based on a new proposed active element. The study encompasses notable proposals during last the decade or more, and provides a platform for a broader future survey on the topic for enhancing the knowledge penetration amongst the researchers in the specified field. A new active element named EXCCII (Extra-X second generation current conveyor) with Buffered Output is found in the study along with its use in a new first-order all-pass section, with possible realization using commercially available IC (AD-844) and results.
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Additional High Input Low Output Impedance Analog Networks
Active and Passive Electronic Components, 2013Co-Authors: Sudhanshu Maheshwari, Bhartendu ChaturvediAbstract:This paper presents some additional high input low Output impedance analog networks realized using a recently introduced single Dual-X Current Conveyor with Buffered Output. The new circuits encompass several all-pass sections of first- and second-order. The voltage-mode proposals benefit from high input impedance and low Output impedance. Nonideality and sensitivity analysis is also performed. The circuit performances are depicted through PSPICE simulations, which show good agreement with theory.
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high input low Output impedance all pass filters using one active element
Iet Circuits Devices & Systems, 2012Co-Authors: Sudhanshu Maheshwari, Bhartendu ChaturvediAbstract:This study presents four new voltage mode first-order all-pass filters using a newly developed single Dual-X current conveyor with Buffered Output. The proposed circuits possess high-input impedance, low-Output impedance and require either two or three passive elements. An application of new circuits is also given in realising the quadrature oscillator. Non-ideal and sensitivity analysis is also performed. The circuit performances are depicted through PSPICE simulations, which show good agreement to theoretical anticipations. Possible realisation using AD-844 along with some experimental results are also given for completeness sake. The new circuits are expected to enhance the already-existing knowledge on the subject.
N. Fong - One of the best experts on this subject based on the ideXlab platform.
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a 1 v 3 8 5 7 ghz wide band vco with differentially tuned accumulation mos varactors for common mode noise rejection in cmos soi technology
IEEE Transactions on Microwave Theory and Techniques, 2003Co-Authors: N. Fong, Jean-olivier Plouchart, Calvin Plett, N. Zamdmer, L Wagner, N. Garry TarrAbstract:In this paper, a 1-V 3.8 - 5.7-GHz wide-band voltage-controlled oscillator (VCO) in a 0.13-/spl mu/m silicon-on-insulator (SOI) CMOS process is presented. This VCO features differentially tuned accumulation MOS varactors that: 1) provide 40% frequency tuning when biased between 0 - 1 V and 2) diminish the adverse effect of high varactor sensitivity through rejection of common-mode noise. This paper shows that, for differential LC VCOs, all low-frequency noise such as flicker noise can be considered to be common-mode noise, and differentially tuned varactors can be used to suppress common-mode noise from being upconverted to the carrier frequency. The noise rejection mechanism is explained, and the technological advantages of SOI over bulk CMOS in this regard is discussed. At 1-MHz offset, the measured phase noise is -121.67 dBc/Hz at 3.8 GHz, and -111.67 dBc/Hz at 5.7 GHz. The power dissipation is between 2.3 - 2.7-mW, depending on the center frequency, and the Buffered Output power is -9 dBm. Due to the noise rejection, the VCO is able to operate at very low voltage and low power. At a supply voltage of 0.75 V, the VCO only dissipates 0.8 mW at 5.5 GHz.
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A low-voltage multi-GHz VCO with 58% tuning range in SOI CMOS
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285), 1Co-Authors: N. Fong, Jean-olivier Plouchart, Calvin Plett, N. Zamdmer, Duixian Liu, Lawrence F. Wagner, G. TarrAbstract:A low-voltage 3.0-5.6 GHz VCO was designed and fabricated in an 0.13 /spl mu/m SOI CMOS process. This VCO features a single-loop horseshoe-shaped inductor and an array of band-switching accumulation MOS (AMOS) varactors. This results in good phase noise and a wide tuning range of 58.7% when tuned between 0 to 1.4 V. At a 1 V Supply (V/sub DD/) and 1 MHz offset, the phase noise is -120 dBc/Hz at 3.0 GHz, and -114.5 dBc/Hz at 5.6 GHz. The power dissipation is between 2 and 3 mW across the whole tuning range. The Buffered Output power is -7 dBm. When VDD is reduced to 0.83 V, the VCO dissipates less than 1 mW at 5.6 GHz.
Bhartendu Chaturvedi - One of the best experts on this subject based on the ideXlab platform.
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Single Active Element Based Cascadable Band-Pass Filters for Low-Q Applications
Journal of Circuits Systems and Computers, 2015Co-Authors: Bhartendu Chaturvedi, Sudhanshu MaheshwariAbstract:The paper presents new single active element based second order band pass filters. The new circuits use single dual-X current conveyor with Buffered Output and five passive components. The proposed circuits enjoy the features of high input impedance and low Output impedance, which are desirable features for voltage-mode circuits. Circuit operation at high frequencies are verified along with non-ideality and parasitic study. The Monte Carlo analysis is also done which justify good sensitivity performances of the proposed circuits. Routh–Hurwitz's stability test is performed to verify the stability of the proposed circuits. For showing the integration aspect, resistorless band-pass filters are also realized. The proposed low-Q filters are useful for cascading. The feature of cascadability is further utilized by showing an application of fourth-order band-pass filter. The performances of the proposed circuits are depicted through Personal Simulation Program with Integrated Circuit Emphasis (PSPICE) simulations, which show good agreement to theoretical applications. The new circuits are expected to enhance the already existing knowledge on the subject.
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Additional High Input Low Output Impedance Analog Networks
Active and Passive Electronic Components, 2013Co-Authors: Sudhanshu Maheshwari, Bhartendu ChaturvediAbstract:This paper presents some additional high input low Output impedance analog networks realized using a recently introduced single Dual-X Current Conveyor with Buffered Output. The new circuits encompass several all-pass sections of first- and second-order. The voltage-mode proposals benefit from high input impedance and low Output impedance. Nonideality and sensitivity analysis is also performed. The circuit performances are depicted through PSPICE simulations, which show good agreement with theory.
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high input low Output impedance all pass filters using one active element
Iet Circuits Devices & Systems, 2012Co-Authors: Sudhanshu Maheshwari, Bhartendu ChaturvediAbstract:This study presents four new voltage mode first-order all-pass filters using a newly developed single Dual-X current conveyor with Buffered Output. The proposed circuits possess high-input impedance, low-Output impedance and require either two or three passive elements. An application of new circuits is also given in realising the quadrature oscillator. Non-ideal and sensitivity analysis is also performed. The circuit performances are depicted through PSPICE simulations, which show good agreement to theoretical anticipations. Possible realisation using AD-844 along with some experimental results are also given for completeness sake. The new circuits are expected to enhance the already-existing knowledge on the subject.
