The Experts below are selected from a list of 90 Experts worldwide ranked by ideXlab platform
Nikil Dutt - One of the best experts on this subject based on the ideXlab platform.
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capps a framework for power performance tradeoffs in Bus Matrix based on chip communication architecture synthesis
IEEE Transactions on Very Large Scale Integration Systems, 2010Co-Authors: Sudeep Pasricha, Younghwan Park, Fadi J Kurdahi, Nikil DuttAbstract:On-chip communication architectures have a significant impact on the power consumption and performance of emerging chip multiprocessor (CMP) applications. However, customization of such architectures for an application requires the exploration of a large design space. Designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper, we present an automated framework for fast system-level, application-specific, power-performance tradeoffs in a Bus Matrix communication architecture synthesis (CAPPS). Our study makes two specific contributions. First, we develop energy models for system-level exploration of Bus Matrix communication architectures. Second, we incorporate these models into a Bus Matrix synthesis flow that enables designers to efficiently explore the power-performance design space of different Bus Matrix configurations. Experimental results show that our energy macromodels incur less than 5% average cycle energy error across 180-65 nm technology libraries. Our early system-level power estimation approach also shows a significant speedup ranging from 1000 to 2000× when compared with detailed gate-level power estimation. Furthermore, on applying our synthesis framework to three industrial networking CMP applications, a tradeoff space that exhibits up to 20% variation in power and up to 40% variation in performance is generated, demonstrating the usefulness of our approach.
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BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007Co-Authors: Sudeep Pasricha, Nikil Dutt, Mohamed Ben-romdhaneAbstract:Modern multiprocessor system-on-chip designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Traditional hierarchical shared Bus communication architectures can only support limited bandwidths and are not scalable for very high-performance designs. Bus Matrix-based communication architectures consist of several parallel Busses which provide a suitable backbone to support high-bandwidth systems but suffer from high-cost overhead due to extensive Bus wiring inside the Matrix. Manual traversal of the vast exploration space to synthesize a minimal cost Bus Matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a Bus Matrix communication architecture, which satisfies all performance constraints in the design and minimizes wire congestion in the Matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9times component savings when compared to a full Bus Matrix, and up to 3.2times savings when compared to a maximally connected reduced Bus Matrix, while satisfying all performance constraints in the design.
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system level power performance trade offs in Bus Matrix communication architecture synthesis
International Conference on Hardware Software Codesign and System Synthesis, 2006Co-Authors: Sudeep Pasricha, Younghwan Park, Fadi J Kurdahi, Nikil DuttAbstract:System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multi-processor system-on-chips (MPSoCs). However, customization of such architectures for an application requires the exploration of a large design space. Thus designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper we present an automated framework for fast system-level, application-specific, power-performance trade-offs in Bus Matrix communication architecture synthesis. Our paper makes two specific contributions. First, we develop energy macro-models for system-level exploration of Bus Matrix communication architectures. Second, we incorporate these macro-models into a Bus Matrix synthesis flow that enables designers to efficiently explore the power-performance design space of different Bus Matrix configurations. Experimental results show that our energy macro-models incur less than 5% average absolute error compared to gate-level models. Furthermore, our Bus Matrix synthesis framework generates a tradeoff space with designs that exhibits an approximately 20% variation in power and 40% variation in performance on an industrial networking MPSoC application, demonstrating the utility of our approach.
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constraint driven Bus Matrix synthesis for mpsoc
Asia and South Pacific Design Automation Conference, 2006Co-Authors: Sudeep Pasricha, Nikil Dutt, Mohamed BenromdhaneAbstract:Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus Matrix based communication architectures consist of several parallel Busses, which provide a suitable backbone to support high bandwidth systems, but suffer from high cost overhead due to extensive Bus wiring inside the Matrix. Manual traversal of the vast exploration space to synthesize a minimal cost Bus Matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a Bus Matrix communication architecture which satisfies all performance constraints in the design and minimizes wire congestion in the Matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9 X component savings when compared to a full Bus Matrix and up to 3.2 X savings when compared to a maximally connected reduced Bus Matrix.
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constraint driven Bus Matrix synthesis for mpsoc
Asia and South Pacific Design Automation Conference, 2006Co-Authors: Sudeep Pasricha, Nikil Dutt, Mohamed BenromdhaneAbstract:Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus Matrix based communication architectures consist of several parallel Buses which provide a suitable backbone to support high bandwidth systems, but suffer from high cost overhead due to extensive Bus wiring inside the Matrix. Manual traversal of the vast exploration space to synthesize a minimal cost Bus Matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a Bus Matrix communication architecture which satisfies all performance constraints in the design and minimizes wire congestion in the Matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9/spl times/ component savings when compared to a full Bus Matrix and up to 3.2/spl times/ savings when compared to a maximally connected reduced Bus Matrix.
Sudeep Pasricha - One of the best experts on this subject based on the ideXlab platform.
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capps a framework for power performance tradeoffs in Bus Matrix based on chip communication architecture synthesis
IEEE Transactions on Very Large Scale Integration Systems, 2010Co-Authors: Sudeep Pasricha, Younghwan Park, Fadi J Kurdahi, Nikil DuttAbstract:On-chip communication architectures have a significant impact on the power consumption and performance of emerging chip multiprocessor (CMP) applications. However, customization of such architectures for an application requires the exploration of a large design space. Designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper, we present an automated framework for fast system-level, application-specific, power-performance tradeoffs in a Bus Matrix communication architecture synthesis (CAPPS). Our study makes two specific contributions. First, we develop energy models for system-level exploration of Bus Matrix communication architectures. Second, we incorporate these models into a Bus Matrix synthesis flow that enables designers to efficiently explore the power-performance design space of different Bus Matrix configurations. Experimental results show that our energy macromodels incur less than 5% average cycle energy error across 180-65 nm technology libraries. Our early system-level power estimation approach also shows a significant speedup ranging from 1000 to 2000× when compared with detailed gate-level power estimation. Furthermore, on applying our synthesis framework to three industrial networking CMP applications, a tradeoff space that exhibits up to 20% variation in power and up to 40% variation in performance is generated, demonstrating the usefulness of our approach.
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BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007Co-Authors: Sudeep Pasricha, Nikil Dutt, Mohamed Ben-romdhaneAbstract:Modern multiprocessor system-on-chip designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Traditional hierarchical shared Bus communication architectures can only support limited bandwidths and are not scalable for very high-performance designs. Bus Matrix-based communication architectures consist of several parallel Busses which provide a suitable backbone to support high-bandwidth systems but suffer from high-cost overhead due to extensive Bus wiring inside the Matrix. Manual traversal of the vast exploration space to synthesize a minimal cost Bus Matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a Bus Matrix communication architecture, which satisfies all performance constraints in the design and minimizes wire congestion in the Matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9times component savings when compared to a full Bus Matrix, and up to 3.2times savings when compared to a maximally connected reduced Bus Matrix, while satisfying all performance constraints in the design.
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system level power performance trade offs in Bus Matrix communication architecture synthesis
International Conference on Hardware Software Codesign and System Synthesis, 2006Co-Authors: Sudeep Pasricha, Younghwan Park, Fadi J Kurdahi, Nikil DuttAbstract:System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multi-processor system-on-chips (MPSoCs). However, customization of such architectures for an application requires the exploration of a large design space. Thus designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper we present an automated framework for fast system-level, application-specific, power-performance trade-offs in Bus Matrix communication architecture synthesis. Our paper makes two specific contributions. First, we develop energy macro-models for system-level exploration of Bus Matrix communication architectures. Second, we incorporate these macro-models into a Bus Matrix synthesis flow that enables designers to efficiently explore the power-performance design space of different Bus Matrix configurations. Experimental results show that our energy macro-models incur less than 5% average absolute error compared to gate-level models. Furthermore, our Bus Matrix synthesis framework generates a tradeoff space with designs that exhibits an approximately 20% variation in power and 40% variation in performance on an industrial networking MPSoC application, demonstrating the utility of our approach.
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constraint driven Bus Matrix synthesis for mpsoc
Asia and South Pacific Design Automation Conference, 2006Co-Authors: Sudeep Pasricha, Nikil Dutt, Mohamed BenromdhaneAbstract:Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus Matrix based communication architectures consist of several parallel Busses, which provide a suitable backbone to support high bandwidth systems, but suffer from high cost overhead due to extensive Bus wiring inside the Matrix. Manual traversal of the vast exploration space to synthesize a minimal cost Bus Matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a Bus Matrix communication architecture which satisfies all performance constraints in the design and minimizes wire congestion in the Matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9 X component savings when compared to a full Bus Matrix and up to 3.2 X savings when compared to a maximally connected reduced Bus Matrix.
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constraint driven Bus Matrix synthesis for mpsoc
Asia and South Pacific Design Automation Conference, 2006Co-Authors: Sudeep Pasricha, Nikil Dutt, Mohamed BenromdhaneAbstract:Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus Matrix based communication architectures consist of several parallel Buses which provide a suitable backbone to support high bandwidth systems, but suffer from high cost overhead due to extensive Bus wiring inside the Matrix. Manual traversal of the vast exploration space to synthesize a minimal cost Bus Matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a Bus Matrix communication architecture which satisfies all performance constraints in the design and minimizes wire congestion in the Matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9/spl times/ component savings when compared to a full Bus Matrix and up to 3.2/spl times/ savings when compared to a maximally connected reduced Bus Matrix.
Maung Than Oo Amanullah - One of the best experts on this subject based on the ideXlab platform.
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Real Power Loss Allocation Using Modified Nodal Equations for Deregulated Power System
IEEE, 2009Co-Authors: Mustafa M. W, Kalam Akhtar, Khalid S. N, Shareef H, Khairuddin, Azhar Bin, Maung Than Oo AmanullahAbstract:This paper introduces a new method to allocate real power loss caused by generators and loads using modified nodal equations. Based on solved load flow results, the method partitions the Y-Bus Matrix to decompose the current of the load Buses as a function of the generators' current and load voltages. Then it uses the modified admittance Matrix to decompose the load voltage dependent term into components of generator dependent terms. By using these two decompositions of current and voltage terms, the real power loss allocations caused by the generators are obtained. Similarly, in case of real power loss allocations caused by the loads, the generator voltage dependent term can be decomposed into components of load dependent terms. Likewise, by using these two decompositions, the real power loss allocations caused by the loads are determined. The proposed method is illustrated on a simple 5-Bus system and tested on the modified IEEE 30-Bus system. The proposed methodology provides reasonable and accurate results to real power loss allocation. Conference title: 19th Australasian Universities Power Engineering Conference: Sustainable Energy Technologies and Systems 27-30 September 2009
Chunghsien Liao - One of the best experts on this subject based on the ideXlab platform.
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allocating the costs of reactive power purchased in an ancillary service market by modified y Bus Matrix method
IEEE Transactions on Power Systems, 2004Co-Authors: Wenchen Chu, Binkwie Chen, Chunghsien LiaoAbstract:In an open accessed transmission system, the costs of each ancillary service will be unbundled. This paper proposes a straightforward method of allocating the costs of reactive power purchased by contract or from a bidding market. This method uses basic circuit theory and partitions the Y-Bus Matrix to decompose the voltage of the load Buses with a view to calculating the reactive power sharing. This method is derived from the system equations without such assumptions as the proportional flow or lossless transmission line.
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allocating the costs of reactive power purchased in an ancillary service market by modified y Bus
2004Co-Authors: Wenchen Chu, Binkwie Chen, Chunghsien LiaoAbstract:In an open accessed transmission system, the costs of each ancillary service will be unbundled. This paper proposes a straightforward method of allocating the costs of reactive power purchased by contract or from a bidding market. This method uses basic circuit theory and partitions the Y-Bus Matrix to decompose the voltage of the load Buses with a view to calculating the reac- tive power sharing. This method is derived from the system equa- tions without such assumptions as the proportional flow or lossless transmission line. Index Terms—Ancillary service, cost allocation, reactive power.
Mohamed Benromdhane - One of the best experts on this subject based on the ideXlab platform.
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constraint driven Bus Matrix synthesis for mpsoc
Asia and South Pacific Design Automation Conference, 2006Co-Authors: Sudeep Pasricha, Nikil Dutt, Mohamed BenromdhaneAbstract:Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus Matrix based communication architectures consist of several parallel Busses, which provide a suitable backbone to support high bandwidth systems, but suffer from high cost overhead due to extensive Bus wiring inside the Matrix. Manual traversal of the vast exploration space to synthesize a minimal cost Bus Matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a Bus Matrix communication architecture which satisfies all performance constraints in the design and minimizes wire congestion in the Matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9 X component savings when compared to a full Bus Matrix and up to 3.2 X savings when compared to a maximally connected reduced Bus Matrix.
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constraint driven Bus Matrix synthesis for mpsoc
Asia and South Pacific Design Automation Conference, 2006Co-Authors: Sudeep Pasricha, Nikil Dutt, Mohamed BenromdhaneAbstract:Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus Matrix based communication architectures consist of several parallel Buses which provide a suitable backbone to support high bandwidth systems, but suffer from high cost overhead due to extensive Bus wiring inside the Matrix. Manual traversal of the vast exploration space to synthesize a minimal cost Bus Matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a Bus Matrix communication architecture which satisfies all performance constraints in the design and minimizes wire congestion in the Matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9/spl times/ component savings when compared to a full Bus Matrix and up to 3.2/spl times/ savings when compared to a maximally connected reduced Bus Matrix.
