The Experts below are selected from a list of 303 Experts worldwide ranked by ideXlab platform
Jarkko Niittylahti - One of the best experts on this subject based on the ideXlab platform.
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scalar metric for temporal locality and estimation of Cache performance
Design Automation and Test in Europe, 2004Co-Authors: Juha Alakarhu, Jarkko NiittylahtiAbstract:A scalar metric for temporal locality is proposed. The metric is based on LRU stack distance. This paper shows that the Cache Hit Rate can be estimated based on the proposed metric (an error of a few percents can be expected). The metric alleviates high-level memory system outlining and enables using stack processing in run-time locality analysis.
Babak Falsafi - One of the best experts on this subject based on the ideXlab platform.
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proactive instruction fetch
International Symposium on Microarchitecture, 2011Co-Authors: Michael Ferdman, Cansu Kaynak, Babak FalsafiAbstract:Fast access requirements preclude building L1 instruction Caches large enough to capture the working set of server workloads. Efforts exist to mitigate limited L1 instruction Cache capacity by relying on the stability and repetitiveness of the instruction stream to predict and prefetch future instruction blocks prior to their use. However, dynamic variation in Cache miss sequences prevents correct and timely prediction, leaving many instruction-fetch stalls exposed, resulting in a key performance bottleneck for servers. We observe that, while the vast majority of application instruction references are amenable to prediction, even minor control-flow variations are amplified by microarcHitectural components, resulting in a major source of instability and randomness that significantly limit prefetcher utility. Control-flow variation disturbs the L1 instruction Cache replacement order and branch predictor state, causing the L1 instruction Cache to randomly filter the instruction stream while the branch predictor and spontaneous hardware interrupts inject the stream with unpredictable noise. Based on this observation, we show that an instruction prefetcher, previously plagued by microarcHitectural instability, becomes nearly perfect when modified to opeRate on the correct-path, retire-order instruction stream. We propose Proactive Instruction Fetch, an instruction prefetch mechanism that achieves higher than 99.5% instruction-Cache Hit Rate, improving server throughput by 27% and nearly matching the performance of a perfect L1 instruction Cache that never misses.
Tulika Mitra - One of the best experts on this subject based on the ideXlab platform.
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instruction Cache locking using temporal reuse profile
Design Automation Conference, 2010Co-Authors: Yun Liang, Tulika MitraAbstract:The performance of most embedded systems is critically dependent on the average memory access latency. Improving the Cache Hit Rate can have significant positive impact on the performance of an application. Modern embedded processors often feature Cache locking mechanisms that allow memory blocks to be locked in the Cache under software control. Cache locking was primarily designed to offer timing predictability for hard real-time applications. Hence, the compiler optimization techniques focus on employing Cache locking to improve worst-case execution time. However, Cache locking can be quite effective in improving the average-case execution time of general embedded applications as well. In this paper, we explore static instruction Cache locking to improve average-case program performance. We introduce temporal reuse profile to accuRately and efficiently model the cost and benefit of locking memory blocks in the Cache. We propose an optimal algorithm and a heuristic approach that use the temporal reuse profile to determine the most beneficial memory blocks to be locked in the Cache. Experimental results show that locking heuristic achieves close to optimal results and can improve the Cache miss Rate by up to 24% across a suite of real-world benchmarks. Moreover, our heuristic provides significant improvement compared to the state-of-the-art locking algorithm both in terms of performance and efficiency.
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Improved Procedure Placement for Set Associative Caches
2010Co-Authors: Yun Liang, Tulika MitraAbstract:The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher Cache Hit Rate can provide significant performance boost to an embedded application. Procedure placement is a popular technique that aims to improve instruction Cache Hit Rate by reducing conflicts in the Cache through compile/link time reordering of procedures. However, existing procedure placement techniques make reordering decisions based on imprecise conflict information. This imprecision leads to limited and sometimes negative performance gain, specially for set-associative Caches. In this paper, we introduce intermediate blocks profile (IBP) to accuRately but compactly model cost-benefit of procedure placement for both direct mapped and set associative Caches. We propose an efficient algorithm that exploits IBP to place procedures in memory such that Cache conflicts are minimized. Experimental results demonstRate that our approach provides substantial improvement in Cache performance over existing procedure placement techniques. Furthermore, we observe that the code layout for a specific Cache configuration is not portable across different Cache configurations. To solve this problem, we propose an algorithm that exploits IBP to place procedures in memory such that the average Cache miss Rate across a set of Cache configurations is minimized
Juha Alakarhu - One of the best experts on this subject based on the ideXlab platform.
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scalar metric for temporal locality and estimation of Cache performance
Design Automation and Test in Europe, 2004Co-Authors: Juha Alakarhu, Jarkko NiittylahtiAbstract:A scalar metric for temporal locality is proposed. The metric is based on LRU stack distance. This paper shows that the Cache Hit Rate can be estimated based on the proposed metric (an error of a few percents can be expected). The metric alleviates high-level memory system outlining and enables using stack processing in run-time locality analysis.
Takuro Sato - One of the best experts on this subject based on the ideXlab platform.
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a smart congestion control mechanism for the green iot sensor enabled information centric networking
Sensors, 2018Co-Authors: Rungrot Sukjaimuk, Quang Ngoc Nguyen, Takuro SatoAbstract:Information-Centric Networking (ICN) is a new Internet arcHitecture design, which is considered as the global-scale Future Internet (FI) paradigm. Though ICN offers considerable benefits over the existing IP-based Internet arcHitecture, its practical deployment in real life still has many challenges, especially in the case of high congestion and limited power in a sensor enabled-network for the Internet of Things (IoT) era. In this paper, we propose a smart congestion control mechanism to diminish the network congestion Rate, reduce sensor power consumptions, and enhance the network performance of ICN at the same time to realize a complete green and efficient ICN-based sensor networking model. The proposed network system uses the chunk-by-chunk aggregated packets according to the content popularity to diminish the number of exchanged packets needed for data transmission. We also design the sensor power-based Cache management stRategy, and an adaptive Markov-based sensor scheduling policy with selective sensing algorithm to further maximize power savings for the sensors. The evaluation results using ndnSIM (a widely-used ICN simulator) show that the proposed model can provide higher network performance efficiency with lower energy consumption for the future Internet by achieving higher throughput with higher Cache Hit Rate and lower Interest packet drop Rate as we increase the number of IoT sensors in ICN.
