The Experts below are selected from a list of 46257 Experts worldwide ranked by ideXlab platform
James B. Kuo - One of the best experts on this subject based on the ideXlab platform.
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a 0 8 v 128 kb four way set associative two level cmos Cache Memory using two stage wordline bitline oriented tag compare wlotc blotc scheme
IEEE Journal of Solid-state Circuits, 2002Co-Authors: Perng-fei Lin, James B. KuoAbstract:This paper reports a 0.8-V 128-kb four-way set-associative two-level CMOS Cache Memory using a novel two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) and sense wordline/bitline (SWL/SBL) tag-sense amplifiers with an eight-transistor (8-T) tag cell in Level 2 (L2) and a 10-T shrunk logic swing (SLS) Memory cell. with the ground/floating (G/F) data sense amplifier in Level 1 (L1) for high-speed operation for low-voltage low-power VLSI system applications. Owing to the reduced loading at the SWL in the new 11-T tag cell using the WLOTC scheme, the 10-T SLS Memory cell with G/F sense amplifier in L1, and the split comparison of the index signal in the 8-T tag cells with SWL/SBL tag sense amplifiers in L2, this 0.8-V Cache Memory implemented in a 1.8-V 0.18-/spl mu/m CMOS technology has a measured L1/L2 hit time of 11.6/20.5 ns at the average dissipation of 0.77 mW at 50 MHz.
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A 0.8V, 9ns, 0.77mW at 50MHz, 128kb, four-way, set-associative, 2-level CMOS Cache Memory using two-stage WLOTC/BLOTC tag-compare scheme and sense wordlines/bitlines (SWL/SBL) tag sense amps with an 8-T tag cell in level 2 and a 10-T shrunk logic swi
2001Co-Authors: James B. Kuo, Perng-fei LinAbstract:This paper presents a 0.8V, 128Kb, four-way, set-associative, 2-level CMOS Cache Memory using a novel two-stage WLOTC/BLOTC tag-compare scheme and sense wordlines/bitlines (SWL/SBL) tag sense amps with an 8-T tag cell in level 2 and a 10-T shrunk logic swing (SLS) Memory cell with the ground/floating (G/F) data sense amp in level 1 for high-speed operation. Owing to the reduced loading at the sense word-line (SWL) in the new 11-T tag cell in L1 using WLOTC scheme and the split comparison of the index signal in the 8-T tag cells with SWL/SBL tag sense amps and the SLS Memory cell with G/F data sense amp in L1, implemented by a 1.8V 0.18µm CMOS technology, this 0.8V Cache Memory has an L1/L2 hit time of 6ns/11ns at the average power dissipation of 0.77mW at 50MHz.
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A 1-V 128-kb four-way set-associative CMOS Cache Memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-Memory (CAM) 10-transistor tag cell
IEEE Journal of Solid-State Circuits, 2001Co-Authors: Perng-fei Lin, James B. KuoAbstract:This paper reports a 1-V 128-kb four-way set-associative CMOS Cache Memory implemented by a 0.18-/spl mu/m CMOS technology using wordline-oriented tag-compare (WLOTC) structure with the 10-transistor tag cell usually for content-addressable Memory (CAM) for low-voltage low-power VLSI system application. Owing to the WLOTC structure with the CAM 10-transistor tag cell for accommodating the one-step hit/miss generation and the dynamic pulse generators for realizing read-enable signals, a small hit access time (3.5 ns), low power consumption (4.1 mW at 50 MHz), and good expansion capability without sacrificing speed have been obtained.
Salman A Avestimehr - One of the best experts on this subject based on the ideXlab platform.
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characterizing the rate Memory tradeoff in Cache networks within a factor of 2
IEEE Transactions on Information Theory, 2019Co-Authors: Qian Yu, Mohammad Ali Maddahali, Salman A AvestimehrAbstract:We consider a basic caching system, where a single server with a database of $N$ files (e.g., movies) is connected to a set of $K$ users through a shared bottleneck link. Each user has a local Cache Memory with a size of $M$ files. The system operates in two phases: a placement phase, where each Cache Memory is populated up to its size from the database, and a following delivery phase, where each user requests a file from the database, and the server is responsible for delivering the requested contents. The objective is to design the two phases to minimize the load (peak or average) of the bottleneck link. We characterize the rate-Memory tradeoff of the above caching system within a factor of 2.00884 for both the peak rate and the average rate (under uniform file popularity), improving the state of the arts that are within a factor of 4 and 4.7, respectively. Moreover, in a practically important case where the number of files ( $N$ ) is large, we exactly characterize the tradeoff for systems with no more than five users and characterize the tradeoff within a factor of 2 otherwise. To establish these results, we develop two new converse bounds that improve over the state of the art.
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characterizing the rate Memory tradeoff in Cache networks within a factor of 2
International Symposium on Information Theory, 2017Co-Authors: Qian Yu, Mohammad Ali Maddahali, Salman A AvestimehrAbstract:We consider a basic caching system, where a single server with a database of N files (e.g. movies) is connected to a set of K users through a shared bottleneck link. Each user has a local Cache Memory with a size of M files. The system operates in two phases: a placement phase, where each Cache Memory is populated up to its size from the database, and a following delivery phase, where each user requests a file from the database, and the server is responsible for delivering the requested contents. The objective is to design the two phases to minimize the load (peak or average) of the bottleneck link. We characterize the rate-Memory tradeoff of the above caching system within a factor of 2.00884 for both the peak rate and the average rate (under uniform file popularity), where the best proved characterization in the current literature gives a factor of 4 and 4.7 respectively. Moreover, in the practically important case where the number of files (N) is large, we exactly characterize the tradeoff for systems with no more than 5 users, and characterize the tradeoff within a factor of 2 otherwise. We establish these results by developing novel information theoretic outer-bounds for the caching problem, which improves the state of the art and gives tight characterization in various cases.
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characterizing the rate Memory tradeoff in Cache networks within a factor of 2
arXiv: Information Theory, 2017Co-Authors: Qian Yu, Mohammad Ali Maddahali, Salman A AvestimehrAbstract:We consider a basic caching system, where a single server with a database of $N$ files (e.g. movies) is connected to a set of $K$ users through a shared bottleneck link. Each user has a local Cache Memory with a size of $M$ files. The system operates in two phases: a placement phase, where each Cache Memory is populated up to its size from the database, and a following delivery phase, where each user requests a file from the database, and the server is responsible for delivering the requested contents. The objective is to design the two phases to minimize the load (peak or average) of the bottleneck link. We characterize the rate-Memory tradeoff of the above caching system within a factor of $2.00884$ for both the peak rate and the average rate (under uniform file popularity), improving state of the arts that are within a factor of $4$ and $4.7$ respectively. Moreover, in a practically important case where the number of files ($N$) is large, we exactly characterize the tradeoff for systems with no more than $5$ users, and characterize the tradeoff within a factor of $2$ otherwise. To establish these results, we develop two new converse bounds that improve over the state of the art.
Perng-fei Lin - One of the best experts on this subject based on the ideXlab platform.
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a 0 8 v 128 kb four way set associative two level cmos Cache Memory using two stage wordline bitline oriented tag compare wlotc blotc scheme
IEEE Journal of Solid-state Circuits, 2002Co-Authors: Perng-fei Lin, James B. KuoAbstract:This paper reports a 0.8-V 128-kb four-way set-associative two-level CMOS Cache Memory using a novel two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) and sense wordline/bitline (SWL/SBL) tag-sense amplifiers with an eight-transistor (8-T) tag cell in Level 2 (L2) and a 10-T shrunk logic swing (SLS) Memory cell. with the ground/floating (G/F) data sense amplifier in Level 1 (L1) for high-speed operation for low-voltage low-power VLSI system applications. Owing to the reduced loading at the SWL in the new 11-T tag cell using the WLOTC scheme, the 10-T SLS Memory cell with G/F sense amplifier in L1, and the split comparison of the index signal in the 8-T tag cells with SWL/SBL tag sense amplifiers in L2, this 0.8-V Cache Memory implemented in a 1.8-V 0.18-/spl mu/m CMOS technology has a measured L1/L2 hit time of 11.6/20.5 ns at the average dissipation of 0.77 mW at 50 MHz.
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A 0.8V, 9ns, 0.77mW at 50MHz, 128kb, four-way, set-associative, 2-level CMOS Cache Memory using two-stage WLOTC/BLOTC tag-compare scheme and sense wordlines/bitlines (SWL/SBL) tag sense amps with an 8-T tag cell in level 2 and a 10-T shrunk logic swi
2001Co-Authors: James B. Kuo, Perng-fei LinAbstract:This paper presents a 0.8V, 128Kb, four-way, set-associative, 2-level CMOS Cache Memory using a novel two-stage WLOTC/BLOTC tag-compare scheme and sense wordlines/bitlines (SWL/SBL) tag sense amps with an 8-T tag cell in level 2 and a 10-T shrunk logic swing (SLS) Memory cell with the ground/floating (G/F) data sense amp in level 1 for high-speed operation. Owing to the reduced loading at the sense word-line (SWL) in the new 11-T tag cell in L1 using WLOTC scheme and the split comparison of the index signal in the 8-T tag cells with SWL/SBL tag sense amps and the SLS Memory cell with G/F data sense amp in L1, implemented by a 1.8V 0.18µm CMOS technology, this 0.8V Cache Memory has an L1/L2 hit time of 6ns/11ns at the average power dissipation of 0.77mW at 50MHz.
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A 1-V 128-kb four-way set-associative CMOS Cache Memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-Memory (CAM) 10-transistor tag cell
IEEE Journal of Solid-State Circuits, 2001Co-Authors: Perng-fei Lin, James B. KuoAbstract:This paper reports a 1-V 128-kb four-way set-associative CMOS Cache Memory implemented by a 0.18-/spl mu/m CMOS technology using wordline-oriented tag-compare (WLOTC) structure with the 10-transistor tag cell usually for content-addressable Memory (CAM) for low-voltage low-power VLSI system application. Owing to the WLOTC structure with the CAM 10-transistor tag cell for accommodating the one-step hit/miss generation and the dynamic pulse generators for realizing read-enable signals, a small hit access time (3.5 ns), low power consumption (4.1 mW at 50 MHz), and good expansion capability without sacrificing speed have been obtained.
Qian Yu - One of the best experts on this subject based on the ideXlab platform.
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characterizing the rate Memory tradeoff in Cache networks within a factor of 2
IEEE Transactions on Information Theory, 2019Co-Authors: Qian Yu, Mohammad Ali Maddahali, Salman A AvestimehrAbstract:We consider a basic caching system, where a single server with a database of $N$ files (e.g., movies) is connected to a set of $K$ users through a shared bottleneck link. Each user has a local Cache Memory with a size of $M$ files. The system operates in two phases: a placement phase, where each Cache Memory is populated up to its size from the database, and a following delivery phase, where each user requests a file from the database, and the server is responsible for delivering the requested contents. The objective is to design the two phases to minimize the load (peak or average) of the bottleneck link. We characterize the rate-Memory tradeoff of the above caching system within a factor of 2.00884 for both the peak rate and the average rate (under uniform file popularity), improving the state of the arts that are within a factor of 4 and 4.7, respectively. Moreover, in a practically important case where the number of files ( $N$ ) is large, we exactly characterize the tradeoff for systems with no more than five users and characterize the tradeoff within a factor of 2 otherwise. To establish these results, we develop two new converse bounds that improve over the state of the art.
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characterizing the rate Memory tradeoff in Cache networks within a factor of 2
International Symposium on Information Theory, 2017Co-Authors: Qian Yu, Mohammad Ali Maddahali, Salman A AvestimehrAbstract:We consider a basic caching system, where a single server with a database of N files (e.g. movies) is connected to a set of K users through a shared bottleneck link. Each user has a local Cache Memory with a size of M files. The system operates in two phases: a placement phase, where each Cache Memory is populated up to its size from the database, and a following delivery phase, where each user requests a file from the database, and the server is responsible for delivering the requested contents. The objective is to design the two phases to minimize the load (peak or average) of the bottleneck link. We characterize the rate-Memory tradeoff of the above caching system within a factor of 2.00884 for both the peak rate and the average rate (under uniform file popularity), where the best proved characterization in the current literature gives a factor of 4 and 4.7 respectively. Moreover, in the practically important case where the number of files (N) is large, we exactly characterize the tradeoff for systems with no more than 5 users, and characterize the tradeoff within a factor of 2 otherwise. We establish these results by developing novel information theoretic outer-bounds for the caching problem, which improves the state of the art and gives tight characterization in various cases.
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characterizing the rate Memory tradeoff in Cache networks within a factor of 2
arXiv: Information Theory, 2017Co-Authors: Qian Yu, Mohammad Ali Maddahali, Salman A AvestimehrAbstract:We consider a basic caching system, where a single server with a database of $N$ files (e.g. movies) is connected to a set of $K$ users through a shared bottleneck link. Each user has a local Cache Memory with a size of $M$ files. The system operates in two phases: a placement phase, where each Cache Memory is populated up to its size from the database, and a following delivery phase, where each user requests a file from the database, and the server is responsible for delivering the requested contents. The objective is to design the two phases to minimize the load (peak or average) of the bottleneck link. We characterize the rate-Memory tradeoff of the above caching system within a factor of $2.00884$ for both the peak rate and the average rate (under uniform file popularity), improving state of the arts that are within a factor of $4$ and $4.7$ respectively. Moreover, in a practically important case where the number of files ($N$) is large, we exactly characterize the tradeoff for systems with no more than $5$ users, and characterize the tradeoff within a factor of $2$ otherwise. To establish these results, we develop two new converse bounds that improve over the state of the art.
Mohammad Ali Maddahali - One of the best experts on this subject based on the ideXlab platform.
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characterizing the rate Memory tradeoff in Cache networks within a factor of 2
IEEE Transactions on Information Theory, 2019Co-Authors: Qian Yu, Mohammad Ali Maddahali, Salman A AvestimehrAbstract:We consider a basic caching system, where a single server with a database of $N$ files (e.g., movies) is connected to a set of $K$ users through a shared bottleneck link. Each user has a local Cache Memory with a size of $M$ files. The system operates in two phases: a placement phase, where each Cache Memory is populated up to its size from the database, and a following delivery phase, where each user requests a file from the database, and the server is responsible for delivering the requested contents. The objective is to design the two phases to minimize the load (peak or average) of the bottleneck link. We characterize the rate-Memory tradeoff of the above caching system within a factor of 2.00884 for both the peak rate and the average rate (under uniform file popularity), improving the state of the arts that are within a factor of 4 and 4.7, respectively. Moreover, in a practically important case where the number of files ( $N$ ) is large, we exactly characterize the tradeoff for systems with no more than five users and characterize the tradeoff within a factor of 2 otherwise. To establish these results, we develop two new converse bounds that improve over the state of the art.
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characterizing the rate Memory tradeoff in Cache networks within a factor of 2
International Symposium on Information Theory, 2017Co-Authors: Qian Yu, Mohammad Ali Maddahali, Salman A AvestimehrAbstract:We consider a basic caching system, where a single server with a database of N files (e.g. movies) is connected to a set of K users through a shared bottleneck link. Each user has a local Cache Memory with a size of M files. The system operates in two phases: a placement phase, where each Cache Memory is populated up to its size from the database, and a following delivery phase, where each user requests a file from the database, and the server is responsible for delivering the requested contents. The objective is to design the two phases to minimize the load (peak or average) of the bottleneck link. We characterize the rate-Memory tradeoff of the above caching system within a factor of 2.00884 for both the peak rate and the average rate (under uniform file popularity), where the best proved characterization in the current literature gives a factor of 4 and 4.7 respectively. Moreover, in the practically important case where the number of files (N) is large, we exactly characterize the tradeoff for systems with no more than 5 users, and characterize the tradeoff within a factor of 2 otherwise. We establish these results by developing novel information theoretic outer-bounds for the caching problem, which improves the state of the art and gives tight characterization in various cases.
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characterizing the rate Memory tradeoff in Cache networks within a factor of 2
arXiv: Information Theory, 2017Co-Authors: Qian Yu, Mohammad Ali Maddahali, Salman A AvestimehrAbstract:We consider a basic caching system, where a single server with a database of $N$ files (e.g. movies) is connected to a set of $K$ users through a shared bottleneck link. Each user has a local Cache Memory with a size of $M$ files. The system operates in two phases: a placement phase, where each Cache Memory is populated up to its size from the database, and a following delivery phase, where each user requests a file from the database, and the server is responsible for delivering the requested contents. The objective is to design the two phases to minimize the load (peak or average) of the bottleneck link. We characterize the rate-Memory tradeoff of the above caching system within a factor of $2.00884$ for both the peak rate and the average rate (under uniform file popularity), improving state of the arts that are within a factor of $4$ and $4.7$ respectively. Moreover, in a practically important case where the number of files ($N$) is large, we exactly characterize the tradeoff for systems with no more than $5$ users, and characterize the tradeoff within a factor of $2$ otherwise. To establish these results, we develop two new converse bounds that improve over the state of the art.
