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C. Webb - One of the best experts on this subject based on the ideXlab platform.

James B. Kuo - One of the best experts on this subject based on the ideXlab platform.

  • a 0 8 v 128 kb four way set associative two level cmos cache memory using two stage Wordline bitline oriented tag compare wlotc blotc scheme
    IEEE Journal of Solid-state Circuits, 2002
    Co-Authors: Perng-fei Lin, James B. Kuo
    Abstract:

    This paper reports a 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using a novel two-stage Wordline/bitline-oriented tag-compare (WLOTC/BLOTC) and sense Wordline/bitline (SWL/SBL) tag-sense amplifiers with an eight-transistor (8-T) tag cell in Level 2 (L2) and a 10-T shrunk logic swing (SLS) memory cell. with the ground/floating (G/F) data sense amplifier in Level 1 (L1) for high-speed operation for low-voltage low-power VLSI system applications. Owing to the reduced loading at the SWL in the new 11-T tag cell using the WLOTC scheme, the 10-T SLS memory cell with G/F sense amplifier in L1, and the split comparison of the index signal in the 8-T tag cells with SWL/SBL tag sense amplifiers in L2, this 0.8-V cache memory implemented in a 1.8-V 0.18-/spl mu/m CMOS technology has a measured L1/L2 hit time of 11.6/20.5 ns at the average dissipation of 0.77 mW at 50 MHz.

  • A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage Wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme
    IEEE Journal of Solid-State Circuits, 2002
    Co-Authors: Perng-fei Lin, James B. Kuo
    Abstract:

    This paper reports a 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using a novel two-stage Wordline/bitline-oriented tag-compare (WLOTC/BLOTC) and sense Wordline/bitline (SWL/SBL) tag-sense amplifiers with an eight-transistor (8-T) tag cell in Level 2 (L2) and a 10-T shrunk logic swing (SLS) memory cell. with the ground/floating (G/F) data sense amplifier in Level 1 (L1) for high-speed operation for low-voltage low-power VLSI system applications. Owing to the reduced loading at the SWL in the new 11-T tag cell using the WLOTC scheme, the 10-T SLS memory cell with G/F sense amplifier in L1, and the split comparison of the index signal in the 8-T tag cells with SWL/SBL tag sense amplifiers in L2, this 0.8-V cache memory implemented in a 1.8-V 0.18-/spl mu/m CMOS technology has a measured L1/L2 hit time of 11.6/20.5 ns at the average dissipation of 0.77 mW at 50 MHz.

Muhammad M. Khellah - One of the best experts on this subject based on the ideXlab platform.

  • capacitive coupling Wordline boosting with self induced v cc collapse for write v min reduction in 22 nm 8t sram
    International Solid-State Circuits Conference, 2012
    Co-Authors: Jaydeep P Kulkarni, Bibiche Geuskens, Tanay Karnik, Muhammad M. Khellah, James W. Tschanz
    Abstract:

    High-performance microprocessors and SoCs include multiple embedded memory arrays used as register files and low-level caches that typically share the same supply voltage as the core [1]. The desire for wide voltage range operation to optimize power and performance dictates the need for SRAM arrays that can achieve both high performance and low minimum voltage of operation (V MIN ). The 8T bitcell (Fig. 13.3.1) is commonly used in these applications because its decoupled read and write ports offer fast read (RD) and write (WR) operations with generally lower V MIN than the 6T bitcell. However, process variations result in mismatches between the pull-up and access devices limiting write V MIN , and/or between read port and keeper transistors limiting read V MIN . Traditional device up-sizing provides diminishing returns at a large area and power cost [2]. In addition to cell upsizing, dynamic assist techniques have been used for V MIN reduction in 6T and 8T arrays — examples include temporary collapse of bitcell voltage for write V MIN reduction and boosting read and write Wordlines requiring careful design of the embedded charge pump and the level shifters [2–4]. In contrast, this paper describes a new capacitive-coupling (CC) write Wordline boost which employs intrinsic coupling capacitance between write bitlines (WBL) and accessed write Wordline (WWL) to boost WWL without the need for a charge pump or complex level shifters. The scheme has a built-in self-induced V CC collapse (SIC) allowing the cell voltage to partially collapse during the write operation, further improving write V MIN . The technique is implemented in a 12KB, 8T cell macro with cell area of 0.238μm2, fabricated in a 22nm CMOS technology (Fig. 13.3.7).

  • ISSCC - Capacitive-coupling Wordline boosting with self-induced V CC collapse for write V MIN reduction in 22-nm 8T SRAM
    2012 IEEE International Solid-State Circuits Conference, 2012
    Co-Authors: Jaydeep P Kulkarni, Bibiche Geuskens, Tanay Karnik, Muhammad M. Khellah, James W. Tschanz
    Abstract:

    High-performance microprocessors and SoCs include multiple embedded memory arrays used as register files and low-level caches that typically share the same supply voltage as the core [1]. The desire for wide voltage range operation to optimize power and performance dictates the need for SRAM arrays that can achieve both high performance and low minimum voltage of operation (V MIN ). The 8T bitcell (Fig. 13.3.1) is commonly used in these applications because its decoupled read and write ports offer fast read (RD) and write (WR) operations with generally lower V MIN than the 6T bitcell. However, process variations result in mismatches between the pull-up and access devices limiting write V MIN , and/or between read port and keeper transistors limiting read V MIN . Traditional device up-sizing provides diminishing returns at a large area and power cost [2]. In addition to cell upsizing, dynamic assist techniques have been used for V MIN reduction in 6T and 8T arrays — examples include temporary collapse of bitcell voltage for write V MIN reduction and boosting read and write Wordlines requiring careful design of the embedded charge pump and the level shifters [2–4]. In contrast, this paper describes a new capacitive-coupling (CC) write Wordline boost which employs intrinsic coupling capacitance between write bitlines (WBL) and accessed write Wordline (WWL) to boost WWL without the need for a charge pump or complex level shifters. The scheme has a built-in self-induced V CC collapse (SIC) allowing the cell voltage to partially collapse during the write operation, further improving write V MIN . The technique is implemented in a 12KB, 8T cell macro with cell area of 0.238μm2, fabricated in a 22nm CMOS technology (Fig. 13.3.7).

  • Wordline bitline pulsing schemes for improving sram cell stability in low vcc 65nm cmos designs
    Symposium on VLSI Circuits, 2006
    Co-Authors: Muhammad M. Khellah, Kevin Zhang, Nam Sung Kim, Dinesh Somasekhar, Gunjan H. Pandya, A. Farhang, C. Webb
    Abstract:

    Pulsed Wordline (PWL) & pulsed bitline (PBL) techniques to improve SRAM cell stabilities in single-Vcc microprocessor designs are evaluated in 65nm CMOS. At 0.7V Vcc, PWL improves cell failure rate by 15times while incurring <1% area overhead. Both PBL & PWL with read-modify-write (PWL-RMW) provide the best improvements (26times) in cell stability, with significant area overheads (4-8%)

  • Wordline & Bitline Pulsing Schemes for Improving SRAM Cell Stability in Low-Vcc 65nm CMOS Designs
    2006 Symposium on VLSI Circuits 2006. Digest of Technical Papers., 1
    Co-Authors: Muhammad M. Khellah, Kevin Zhang, Nam Sung Kim, Dinesh Somasekhar, Gunjan H. Pandya, A. Farhang, C. Webb
    Abstract:

    Pulsed Wordline (PWL) & pulsed bitline (PBL) techniques to improve SRAM cell stabilities in single-Vcc microprocessor designs are evaluated in 65nm CMOS. At 0.7V Vcc, PWL improves cell failure rate by 15times while incurring

Perng-fei Lin - One of the best experts on this subject based on the ideXlab platform.

  • a 0 8 v 128 kb four way set associative two level cmos cache memory using two stage Wordline bitline oriented tag compare wlotc blotc scheme
    IEEE Journal of Solid-state Circuits, 2002
    Co-Authors: Perng-fei Lin, James B. Kuo
    Abstract:

    This paper reports a 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using a novel two-stage Wordline/bitline-oriented tag-compare (WLOTC/BLOTC) and sense Wordline/bitline (SWL/SBL) tag-sense amplifiers with an eight-transistor (8-T) tag cell in Level 2 (L2) and a 10-T shrunk logic swing (SLS) memory cell. with the ground/floating (G/F) data sense amplifier in Level 1 (L1) for high-speed operation for low-voltage low-power VLSI system applications. Owing to the reduced loading at the SWL in the new 11-T tag cell using the WLOTC scheme, the 10-T SLS memory cell with G/F sense amplifier in L1, and the split comparison of the index signal in the 8-T tag cells with SWL/SBL tag sense amplifiers in L2, this 0.8-V cache memory implemented in a 1.8-V 0.18-/spl mu/m CMOS technology has a measured L1/L2 hit time of 11.6/20.5 ns at the average dissipation of 0.77 mW at 50 MHz.

  • A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage Wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme
    IEEE Journal of Solid-State Circuits, 2002
    Co-Authors: Perng-fei Lin, James B. Kuo
    Abstract:

    This paper reports a 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using a novel two-stage Wordline/bitline-oriented tag-compare (WLOTC/BLOTC) and sense Wordline/bitline (SWL/SBL) tag-sense amplifiers with an eight-transistor (8-T) tag cell in Level 2 (L2) and a 10-T shrunk logic swing (SLS) memory cell. with the ground/floating (G/F) data sense amplifier in Level 1 (L1) for high-speed operation for low-voltage low-power VLSI system applications. Owing to the reduced loading at the SWL in the new 11-T tag cell using the WLOTC scheme, the 10-T SLS memory cell with G/F sense amplifier in L1, and the split comparison of the index signal in the 8-T tag cells with SWL/SBL tag sense amplifiers in L2, this 0.8-V cache memory implemented in a 1.8-V 0.18-/spl mu/m CMOS technology has a measured L1/L2 hit time of 11.6/20.5 ns at the average dissipation of 0.77 mW at 50 MHz.

Dinesh Somasekhar - One of the best experts on this subject based on the ideXlab platform.

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