The Experts below are selected from a list of 549 Experts worldwide ranked by ideXlab platform

Tayfun Akin - One of the best experts on this subject based on the ideXlab platform.

  • The advanced MEMS (aMEMS) process for fabricating Wafer level vacuum packaged SOI-MEMS devices with embedded vertical feedthroughs
    2015 Transducers - 2015 18th International Conference on Solid-State Sensors Actuators and Microsystems (TRANSDUCERS), 2015
    Co-Authors: Mustafa Mert Torunbalci, Said Emre Alper, Tayfun Akin
    Abstract:

    This paper presents a novel, inherently simple and low-cost fabrication and hermetic packaging method developed for SOI-MEMS devices, where an SOI Wafer is used for the fabrication of MEMS structures as well as vertical feedthroughs, while a glass Cap Wafer is used for hermetic enCapsulation and routing metallization. Glass-to-silicon anodically bonded seals yield a very stable cavity pressure of 150 mTorr after 15 days. The shear strength of the fabricated packages is above 7 MPa. Temperature cycling and ultra-high temperature shock tests results in no degradation in the hermeticity of the packaged chips.

  • A method for Wafer level hermetic packaging of SOI-MEMS devices with embedded vertical feedthroughs using advanced MEMS process
    Journal of Micromechanics and Microengineering, 2015
    Co-Authors: Mustafa Mert Torunbalci, Said Emre Alper, Tayfun Akin
    Abstract:

    This paper presents a novel, inherently simple, and low-cost fabrication and hermetic packaging method developed for SOI-MEMS devices, where a single SOI Wafer is used for the fabrication of MEMS structures as well as vertical feedthroughs, while a single glass Cap Wafer is used for hermetic enCapsulation and routing metallization. Hermetic enCapsulation can be achieved either with the silicon-glass anodic or Au-Si eutectic bonding techniques. The dies sealed with anodic and Au-Si eutectic bonding provide a low vertical feedthrough resistance around 50. Glass-to-silicon anodically and Au-Si eutectic bonded seals yield a very stable cavity pressure below 10 mTorr with thin-film getters, which are measured to be stable even after 311 d. The package pressure can be adjusted from 5 mTorr to 20 Torr by using different outgassing, cavity depth, and gettering options. The packaging yield is observed to be around 64% and 84% for the anodic and Au-Si eutectic packages, respectively. The average shear strength of the anodic and eutectic packages is measured to be higher than 17 MPa and 42 MPa, respectively. Temperature cycling, high temperature storage, and ultra-high temperature shock tests result in no degradation in the hermeticity of the packaged chips, proving perfect thermal reliability.

  • A novel fabrication and Wafer level hermetic sealing method for SOI-MEMS devices using SOI Cap Wafers
    2015 28th IEEE International Conference on Micro Electro Mechanical Systems (MEMS), 2015
    Co-Authors: Mustafa Mert Torunbalci, Said Emre Alper, Tayfun Akin
    Abstract:

    This paper presents a novel and inherently simple all-silicon fabrication and hermetic packaging method developed for SOI-MEMS devices, enabling lead transfer using vertical feedthroughs formed on an SOI Cap Wafer. The processes of the SOI Cap Wafer and the SOI-MEMS Wafer require a total of five inherently-simple mask steps, providing a combined process and packaging yield as high as 95%. The hermetic enCapsulation is achieved by Au-Si eutectic bonding at 400°C. The package pressure is measured as 1 Torr without any getter activation, and the package is proved to remain hermetic even after various temperature cycling tests. The shear strength of the fabricated chips is measured to be above 15 MPa, indicating a mechanically strong bonding.

  • A Method of Fabricating Vacuum Packages with Vertical Feedthroughs in a Wafer Level Anodic Bonding Process
    Procedia Engineering, 2014
    Co-Authors: Mustafa Mert Torunbalci, Said Emre Alper, Tayfun Akin
    Abstract:

    Abstract This paper presents a new method for Wafer level vacuum packaging of MEMS devices using anodic bonding together with vertical feedthroughs formed on an SOI Cap Wafer, eliminating the need for any sealing material or any complex via-refill or trench-refill vertical feedthrough steps. The packaging yield is experimentally verified to be above 95%, and the cavity pressure is characterized to be as low as 1 mTorr with the help of a thin-film getter. The shear strength of several packages is measured to be above 15 MPa.

  • Microwave Characterization of a Wafer-Level Packaging Approach for RF MEMS Devices Using Glass Frit Bonding
    IEEE Sensors Journal, 2014
    Co-Authors: Ilker Comart, Kagan Topalli, Simsek Demir, Tayfun Akin
    Abstract:

    This paper presents the microwave characterization of a Wafer level packaging approach for RF MEMS devices, using glass frit as the bonding material. Coplanar waveguide transmission lines are packaged by silicon Caps to carry out the RF characterization of the package structure. Prior to bonding of the Cap on the transmission lines, Cap Wafers are bulk micromachined to form the cavities for housing the device to be packaged and pad windows to access the RF ports of the devices. Lateral feedthroughs are designed under the glass frit ring transitions in order to decrease the impedance loading effect of the silicon Cap and the glass frit ring. The package is implemented using both high and low resistive silicon Wafers in order to assess the microwave effects of Cap Wafer. A circuit model is used to extract the parameters of the feedthrough from the RF measurements. The loss of the feedthrough is measured to be 0.1 dB/transition at 10 GHz for high resistive silicon Caps demonstrating the viability of glass frit in the packaging of RF MEMS devices.

C S Premachandran - One of the best experts on this subject based on the ideXlab platform.

  • Fabrication and Testing of a Wafer-Level Vacuum Package for MEMS Device
    IEEE Transactions on Advanced Packaging, 2009
    Co-Authors: C S Premachandran, Ser Choong Chong, Ranganathan Nagarajan
    Abstract:

    A Wafer-level vacuum package with getters deposited on the Cap Wafer is developed for an accelerometer device. An accelerometer Wafer and Cap Wafer is bonded together in a vacuum of 1 mtorr and is characterized using a micro-electro-mechanical systems (MEMS) motion analyzer (MMA). Vacuum inside the package is measured indirectly by measuring the Q-factor response of the accelerometer structure inside the package. The obtained results indicated that there is variation from the center to the edge of the Wafer. This may be due to difference in the outgassing of the package. Different reliability tests on the Wafer-level package showed the package is robust to the reliability conditions. A progressive test on the Q-factor for different cycles of reliability test proved that there is no shift in the measurement value. A 3-D Wafer-level package for accelerometer device is also developed to meet the requirements of vacuum packaging. Hermeticity and CV test showed no degradation in the device performance when subjected to reliability tests.

  • A novel, Wafer-level stacking method for low-chip yield and non-uniform, chip-size Wafers for MEMS and 3D SIP applications
    2008 58th Electronic Components and Technology Conference, 2008
    Co-Authors: C S Premachandran, Myo Ei Pa Pa, Kelvin Chen, Ahmad Khairyanto, Michelle Chew, Won Kyoung Choi
    Abstract:

    Stacking of Wafers with low chip-yield and non uniform chips size is developed for MEMS and 3D packaging applications. Stacking of MEMS and ASIC Wafers one over other is difficult due to difference in chip yield and chip size. A Cap Wafer which is used for sealing the MEMS Wafer in the Wafer level package (WLP) is used for stacking the known good dice from MEMS Wafer. Cavities and through silicon vias (TSV) are formed on a support Wafer which matches with the ASIC (electronics) Wafer. Based on the mapping of the ASIC Wafer, a known good die from MEMS Wafer is picked and attached into the support Wafer. MEMS devices are attached in to the support Wafer either by face down or face up with respect to ASIC chip. Redistribution lay outs are made on the ASIC Wafer to match the pads configuration of the MEMS and ASIC Wafer. The completed support Wafer with MEMS devices in the cavity is bonded with ASIC Wafer in a Wafer bonder for final assembly. Since through hole vias are formed on the support Wafer there is no need to etch through silicon via on either MEMS or AISC Wafer. A hermetically sealed MEMS chip with ASIC one over other is assembled to meet the final real estate reduction of the package size. A stacking approach for low yield and non uniform chip size Wafers is demonstrated.

  • A novel, Wafer-level stacking method for low-chip yield and non-uniform, chip-size Wafers for MEMS and 3D SIP applications
    Proceedings - Electronic Components and Technology Conference, 2008
    Co-Authors: C S Premachandran, Myo Ei Pa Pa, Kelvin Chen, Ahmad Khairyanto, John Lau, Xie Ling, Michelle Chew, Kyoung Choi Won
    Abstract:

    Stacking of Wafers with low chip-yield and non uniform chips size is developed for MEMS and 3D packaging applications. Stacking of MEMS and ASIC Wafers one over other is difficult due to difference in chip yield and chip size. A Cap Wafer which is used for sealing the MEMS Wafer in the Wafer level package (WLP) is used for stacking the known good dice from MEMS Wafer. Cavities and through silicon vias (TSV) are formed on a support Wafer which matches with the ASIC (Electronics) Wafer. Based on the mapping of the ASIC Wafer, a known good die from MEMS Wafer is picked and attached into the support Wafer. MEMS devices are attached in to the support Wafer either by face down or face up with respect to ASIC chip. Redistribution lay outs are made on the ASIC Wafer to match the pads configuration of the MEMS and ASIC Wafer. The completed support Wafer with MEMS devices in the cavity is bonded with ASIC Wafer in a Wafer bonder for final assembly. Since through hole vias are formed on the support Wafer there is no need to etch through silicon via on either MEMS or AISC Wafer. A hermetically sealed MEMS chip with ASIC one over other is assembled to meet the final real estate reduction of the package size. A stacking approach for low yield and non uniform chip size Wafers is demonstrated.

  • C2W bonding method for MEMS applications
    2008 10th Electronics Packaging Technology Conference, 2008
    Co-Authors: Chen Wei Sheng Kelvin, C S Premachandran, Choi Won Kyoung, Ong Siong Chiew Xie Ling, Ahmad Khairyanto Bin Ratmin, Myo Ei Pa Pa
    Abstract:

    A low temperature C2W (Chip to Wafer) bonding method is developed for integrating MEMS and electronics into a Wafer level package. The diced known good MEMS chip is picked and bonded onto an ASIC Wafer using an In based low temperature solder below 200 degC. The C2W bonded MEMS and ASIC Wafer is sealed with a Cap Wafer. The sealed package is characterized for hermeticity and shear strength and found to meet the minimum requirements for a good sealing and bonding.

  • Design, fabrication and testing of Wafer level vacuum package for MEMS device
    56th Electronic Components and Technology Conference 2006, 2006
    Co-Authors: C S Premachandran, Ser Choong Chong, R. Nagarajan
    Abstract:

    A Wafer level vacuum package with getters deposited on the Cap Wafer is developed for an accelerometer device. An accelerometer Wafer and Cap Wafer is bonded together in a vacuum of 1 milli torr and is characterized using a MEMS motion analyzer (MMA). Vacuum inside the package is measured indirectly by measuring the Q factor response of the accelerometer structure inside the package. The obtained results indicated that there is variation from the center to the edge of the Wafer. This may be due to difference in the outgassing of the package. Different reliability tests on the Wafer level package showed the package is robust to the reliability conditions. A progressive test on Q factor for different cycles of reliability test proven that there is no shift in the measurement value. A 3D Wafer level package for accelerometer device is also developed to meet the requirements of vacuum packaging. Hermeticity and CV test showed that no degradation in the device performance when subjected to reliability tests

Yuelin Wang - One of the best experts on this subject based on the ideXlab platform.

  • Wafer-Level Vacuum Packaging for MEMS Resonators Using Glass Frit Bonding
    Journal of Microelectromechanical Systems, 2012
    Co-Authors: Guoqiang Wu, Dehui Xu, Bin Xiong, Yuchen Wang, Yuelin Wang
    Abstract:

    A Wafer-level vacuum package with silicon bumps and electrical feedthroughs on the Cap Wafer is developed for a microelectromechanical systems (MEMS) resonator device. A MEMS resonator Wafer and a Cap Wafer are bonded together in a vacuum chamber using glass frit bonding. The Cap Wafer not only provides a vacuum chamber to protect the movable resonator structure and improve the resonant performance but also realizes the redistribution of the electrical feedthroughs by using the silicon bumps. The silicon bumps provide vertical interconnections between the Cap Wafer and the resonator Wafer, which realizes the bonding pads “transferring” from the resonator Wafer to the Cap Wafer. A gold-aluminum eutectic is used to ensure electrical contacts between the Cap Wafer and the device Wafer. The device fabrication and glass frit hermetic bonding process as well as the packaged MEMS resonator characterization are presented in this paper. Experimental results show that the Wafer-level vacuum-packaged MEMS resonator results in over 100× higher quality factor (Q) than the resonator vibrating in atmosphere pressure, which confirms the transmission performance improvement due to vacuum packaging. Vacuum inside the package is measured indirectly by measuring the Q of the MEMS resonator inside the package. The experimental results indicate that vacuum about 1 mbar can be sealed in this approach.

  • Wafer level vacuum packaged resonator with in-situ Au-Al eutectic Re-Distribution layer
    SENSORS 2012 IEEE, 2012
    Co-Authors: Guoqiang Wu, Dehui Xu, Bin Xiong, Errong Jing, Yuelin Wang
    Abstract:

    In this paper, a Wafer level vacuum packaged resonator with in-situ Au-Al eutectic Re-Distribution layer is demonstrated. A Cap Wafer with silicon bumps and electrical feedthroughs is bonded together with a MEMS resonator Wafer using Wafer level glass frit bonding technology. The silicon bumps provide close contact for the aluminum layer on the Cap Wafer and the gold layer on the device Wafer, on which a gold-aluminum (Au-Al) eutectic is formed. The in-situ Au-Al eutectic layer achieve electrical interconnections between the Cap Wafer and the device Wafer, which realizes the redistribution of the electrical feedthroughs of the MEMS resonator on the Cap Wafer. The formation mechanism of the Au-Al eutectic is illustrated. The Au-Al eutectic is observed through the FD3/SEM and IR images and is analyzed using EDX. The measured dynamic performance of the packaged MEMS resonator is presented in this paper. Experimental results show that the Wafer-level vacuum packaged MEMS resonator results in over 100× higher quality factor (Q) than the resonator vibrating in atmosphere pressure. The experimental results indicate that vacuum about 3 mbar can be sealed in this approach.

  • Redistribution of Electrical Interconnections for Three-Dimensional Wafer-Level Packaging With Silicon Bumps
    IEEE Electron Device Letters, 2012
    Co-Authors: Guoqiang Wu, Dehui Xu, Bin Xiong, Yuelin Wang
    Abstract:

    In this letter, an approach to the redistribution of electrical interconnections is investigated for potential application in 3-D Wafer-level packaging. A Cap Wafer with silicon bumps and electrical feedthroughs is bonded together with a device Wafer using Wafer-level glass-frit bonding technology. During the bonding process, the mechanical bond is performed by glass-frit bonding to form hermetic packaging. Simultaneously, the silicon bumps provide close contact for the electrical feedthroughs on the Cap Wafer and the metal pads on the device Wafer, on which a gold-aluminum eutectic is formed to achieve electrical interconnections between the Cap Wafer and the device Wafer. Moreover, the silicon bumps provide a way to control well the height of the bonding materials. This process not only realizes a Wafer-level hermetic sealing but also achieves the redistribution of electrical interconnections. Application of this approach for a high performance MEMS resonator is demonstrated, which illustrates the feasibility of this process.

  • Wafer-Level Vacuum Packaging of Micromachined Thermoelectric IR Sensors
    IEEE Transactions on Advanced Packaging, 2010
    Co-Authors: Dehui Xu, Bin Xiong, Errong Jing, Yuelin Wang
    Abstract:

    In the trend towards low-cost, high-performance, and miniaturization, a Wafer-level vacuum package is developed for micromachined thermoelectric infrared (IR) sensor. An IR sensor Wafer and a Cap Wafer are bonded together in a vacuum chamber using Au-Au thermocompression bonding, where the Cap Wafer not only protects the floating thermopile structure but also selects IR light for the sensor. The device fabrication and Au-Au thermocompression hermetic bonding process as well as the packaged IR sensor characterization is presented in this paper. Experimental results show that the Wafer-level vacuum packaged IR sensor has a four times higher responsivity and detectivity than the IR sensor with atmosphere pressure package, which confirms the IR performance improvement due to vacuum packaging. IR microscope image of the packaged device proved that the Au-Au thermocompression bonding process is compatible to the handling of fragile micromachined thermopile structure. Average leak rate and shear strength are, respectively, 3.9 × 10-9 atm cc/s and 16.709 Kgf, which shows that the Au-Au thermocompression hermetic bonding is suitable for the Wafer-level vacuum packaging of micromachined thermoelectric IR sensor.

Mustafa Mert Torunbalci - One of the best experts on this subject based on the ideXlab platform.

  • The advanced MEMS (aMEMS) process for fabricating Wafer level vacuum packaged SOI-MEMS devices with embedded vertical feedthroughs
    2015 Transducers - 2015 18th International Conference on Solid-State Sensors Actuators and Microsystems (TRANSDUCERS), 2015
    Co-Authors: Mustafa Mert Torunbalci, Said Emre Alper, Tayfun Akin
    Abstract:

    This paper presents a novel, inherently simple and low-cost fabrication and hermetic packaging method developed for SOI-MEMS devices, where an SOI Wafer is used for the fabrication of MEMS structures as well as vertical feedthroughs, while a glass Cap Wafer is used for hermetic enCapsulation and routing metallization. Glass-to-silicon anodically bonded seals yield a very stable cavity pressure of 150 mTorr after 15 days. The shear strength of the fabricated packages is above 7 MPa. Temperature cycling and ultra-high temperature shock tests results in no degradation in the hermeticity of the packaged chips.

  • A method for Wafer level hermetic packaging of SOI-MEMS devices with embedded vertical feedthroughs using advanced MEMS process
    Journal of Micromechanics and Microengineering, 2015
    Co-Authors: Mustafa Mert Torunbalci, Said Emre Alper, Tayfun Akin
    Abstract:

    This paper presents a novel, inherently simple, and low-cost fabrication and hermetic packaging method developed for SOI-MEMS devices, where a single SOI Wafer is used for the fabrication of MEMS structures as well as vertical feedthroughs, while a single glass Cap Wafer is used for hermetic enCapsulation and routing metallization. Hermetic enCapsulation can be achieved either with the silicon-glass anodic or Au-Si eutectic bonding techniques. The dies sealed with anodic and Au-Si eutectic bonding provide a low vertical feedthrough resistance around 50. Glass-to-silicon anodically and Au-Si eutectic bonded seals yield a very stable cavity pressure below 10 mTorr with thin-film getters, which are measured to be stable even after 311 d. The package pressure can be adjusted from 5 mTorr to 20 Torr by using different outgassing, cavity depth, and gettering options. The packaging yield is observed to be around 64% and 84% for the anodic and Au-Si eutectic packages, respectively. The average shear strength of the anodic and eutectic packages is measured to be higher than 17 MPa and 42 MPa, respectively. Temperature cycling, high temperature storage, and ultra-high temperature shock tests result in no degradation in the hermeticity of the packaged chips, proving perfect thermal reliability.

  • A novel fabrication and Wafer level hermetic sealing method for SOI-MEMS devices using SOI Cap Wafers
    2015 28th IEEE International Conference on Micro Electro Mechanical Systems (MEMS), 2015
    Co-Authors: Mustafa Mert Torunbalci, Said Emre Alper, Tayfun Akin
    Abstract:

    This paper presents a novel and inherently simple all-silicon fabrication and hermetic packaging method developed for SOI-MEMS devices, enabling lead transfer using vertical feedthroughs formed on an SOI Cap Wafer. The processes of the SOI Cap Wafer and the SOI-MEMS Wafer require a total of five inherently-simple mask steps, providing a combined process and packaging yield as high as 95%. The hermetic enCapsulation is achieved by Au-Si eutectic bonding at 400°C. The package pressure is measured as 1 Torr without any getter activation, and the package is proved to remain hermetic even after various temperature cycling tests. The shear strength of the fabricated chips is measured to be above 15 MPa, indicating a mechanically strong bonding.

  • A Method of Fabricating Vacuum Packages with Vertical Feedthroughs in a Wafer Level Anodic Bonding Process
    Procedia Engineering, 2014
    Co-Authors: Mustafa Mert Torunbalci, Said Emre Alper, Tayfun Akin
    Abstract:

    Abstract This paper presents a new method for Wafer level vacuum packaging of MEMS devices using anodic bonding together with vertical feedthroughs formed on an SOI Cap Wafer, eliminating the need for any sealing material or any complex via-refill or trench-refill vertical feedthrough steps. The packaging yield is experimentally verified to be above 95%, and the cavity pressure is characterized to be as low as 1 mTorr with the help of a thin-film getter. The shear strength of several packages is measured to be above 15 MPa.

  • Gold-tin eutectic bonding for hermetic packaging of MEMS devices with vertical feedthroughs
    SENSORS 2014 IEEE, 2014
    Co-Authors: Mustafa Mert Torunbalci, Said Emre Alper, Eyup Can Demir, Inci Donmez, Tayfun Akin
    Abstract:

    This paper presents a new method for Wafer-level hermetic enCapsulation of MEMS devices using low-temperature (280 to 300°C) Au-Sn eutectic bonding applied to the recently developed advanced MEMS (A-MEMS) process of the METU-MEMS Research Center, which uses an SOI Cap Wafer with vertical feedthroughs that does not need any complex via-refill or trench-refill process steps. The Au-Sn eutectic bonding process is achieved at 300°C with a bond pressure of 2 MPa by using a sealing alloy thickness less than 1.5 μm. The package pressure is characterized to be around 250 mTorr, without any getter activation. The remelting temperature of the Au-Sn bonding interface is measured by using differential scanning calorimetry (DSC) analysis and found to be around 280°C, verifying that the bonding is achieved at the desired eutectic composition (80% Au and 20% Sn), also confirmed by the energy dispersive X-ray spectroscopy (EDS) analysis. The shear strengths of several packages are measured to be above 20 MPa, indicating a mechanically-strong bonding. The robustness of the packages is also tested by subjecting them to high temperature storage at 200°C for 24 hours, and no degradation is observed in the hermeticity of the packages at the end of this period.

Said Emre Alper - One of the best experts on this subject based on the ideXlab platform.

  • The advanced MEMS (aMEMS) process for fabricating Wafer level vacuum packaged SOI-MEMS devices with embedded vertical feedthroughs
    2015 Transducers - 2015 18th International Conference on Solid-State Sensors Actuators and Microsystems (TRANSDUCERS), 2015
    Co-Authors: Mustafa Mert Torunbalci, Said Emre Alper, Tayfun Akin
    Abstract:

    This paper presents a novel, inherently simple and low-cost fabrication and hermetic packaging method developed for SOI-MEMS devices, where an SOI Wafer is used for the fabrication of MEMS structures as well as vertical feedthroughs, while a glass Cap Wafer is used for hermetic enCapsulation and routing metallization. Glass-to-silicon anodically bonded seals yield a very stable cavity pressure of 150 mTorr after 15 days. The shear strength of the fabricated packages is above 7 MPa. Temperature cycling and ultra-high temperature shock tests results in no degradation in the hermeticity of the packaged chips.

  • A method for Wafer level hermetic packaging of SOI-MEMS devices with embedded vertical feedthroughs using advanced MEMS process
    Journal of Micromechanics and Microengineering, 2015
    Co-Authors: Mustafa Mert Torunbalci, Said Emre Alper, Tayfun Akin
    Abstract:

    This paper presents a novel, inherently simple, and low-cost fabrication and hermetic packaging method developed for SOI-MEMS devices, where a single SOI Wafer is used for the fabrication of MEMS structures as well as vertical feedthroughs, while a single glass Cap Wafer is used for hermetic enCapsulation and routing metallization. Hermetic enCapsulation can be achieved either with the silicon-glass anodic or Au-Si eutectic bonding techniques. The dies sealed with anodic and Au-Si eutectic bonding provide a low vertical feedthrough resistance around 50. Glass-to-silicon anodically and Au-Si eutectic bonded seals yield a very stable cavity pressure below 10 mTorr with thin-film getters, which are measured to be stable even after 311 d. The package pressure can be adjusted from 5 mTorr to 20 Torr by using different outgassing, cavity depth, and gettering options. The packaging yield is observed to be around 64% and 84% for the anodic and Au-Si eutectic packages, respectively. The average shear strength of the anodic and eutectic packages is measured to be higher than 17 MPa and 42 MPa, respectively. Temperature cycling, high temperature storage, and ultra-high temperature shock tests result in no degradation in the hermeticity of the packaged chips, proving perfect thermal reliability.

  • A novel fabrication and Wafer level hermetic sealing method for SOI-MEMS devices using SOI Cap Wafers
    2015 28th IEEE International Conference on Micro Electro Mechanical Systems (MEMS), 2015
    Co-Authors: Mustafa Mert Torunbalci, Said Emre Alper, Tayfun Akin
    Abstract:

    This paper presents a novel and inherently simple all-silicon fabrication and hermetic packaging method developed for SOI-MEMS devices, enabling lead transfer using vertical feedthroughs formed on an SOI Cap Wafer. The processes of the SOI Cap Wafer and the SOI-MEMS Wafer require a total of five inherently-simple mask steps, providing a combined process and packaging yield as high as 95%. The hermetic enCapsulation is achieved by Au-Si eutectic bonding at 400°C. The package pressure is measured as 1 Torr without any getter activation, and the package is proved to remain hermetic even after various temperature cycling tests. The shear strength of the fabricated chips is measured to be above 15 MPa, indicating a mechanically strong bonding.

  • A Method of Fabricating Vacuum Packages with Vertical Feedthroughs in a Wafer Level Anodic Bonding Process
    Procedia Engineering, 2014
    Co-Authors: Mustafa Mert Torunbalci, Said Emre Alper, Tayfun Akin
    Abstract:

    Abstract This paper presents a new method for Wafer level vacuum packaging of MEMS devices using anodic bonding together with vertical feedthroughs formed on an SOI Cap Wafer, eliminating the need for any sealing material or any complex via-refill or trench-refill vertical feedthrough steps. The packaging yield is experimentally verified to be above 95%, and the cavity pressure is characterized to be as low as 1 mTorr with the help of a thin-film getter. The shear strength of several packages is measured to be above 15 MPa.

  • Gold-tin eutectic bonding for hermetic packaging of MEMS devices with vertical feedthroughs
    SENSORS 2014 IEEE, 2014
    Co-Authors: Mustafa Mert Torunbalci, Said Emre Alper, Eyup Can Demir, Inci Donmez, Tayfun Akin
    Abstract:

    This paper presents a new method for Wafer-level hermetic enCapsulation of MEMS devices using low-temperature (280 to 300°C) Au-Sn eutectic bonding applied to the recently developed advanced MEMS (A-MEMS) process of the METU-MEMS Research Center, which uses an SOI Cap Wafer with vertical feedthroughs that does not need any complex via-refill or trench-refill process steps. The Au-Sn eutectic bonding process is achieved at 300°C with a bond pressure of 2 MPa by using a sealing alloy thickness less than 1.5 μm. The package pressure is characterized to be around 250 mTorr, without any getter activation. The remelting temperature of the Au-Sn bonding interface is measured by using differential scanning calorimetry (DSC) analysis and found to be around 280°C, verifying that the bonding is achieved at the desired eutectic composition (80% Au and 20% Sn), also confirmed by the energy dispersive X-ray spectroscopy (EDS) analysis. The shear strengths of several packages are measured to be above 20 MPa, indicating a mechanically-strong bonding. The robustness of the packages is also tested by subjecting them to high temperature storage at 200°C for 24 hours, and no degradation is observed in the hermeticity of the packages at the end of this period.