The Experts below are selected from a list of 7068 Experts worldwide ranked by ideXlab platform
Shoji Kawahito - One of the best experts on this subject based on the ideXlab platform.
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A high-speed, high-sensitivity digital CMOS image sensor with a global shutter and 12-bit column-parallel cyclic A/D converters
IEEE Journal of Solid-State Circuits, 2007Co-Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji KawahitoAbstract:This paper presents a high-speed, high-sensitivity 512times512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a Charge Amplifier for high Charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-mum CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel Charge Amplifier achieves the optical sensitivity of 19.9 V/lxmiddots. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8mVrms, and the resulting signal dynamic range is 60 dB
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a high speed high sensitivity digital cmos image sensor with a global shutter and 12 bit column parallel cyclic a d converters
Symposium on VLSI Circuits, 2007Co-Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji KawahitoAbstract:This paper presents a high-speed, high-sensitivity 512x512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a Charge Amplifier for high Charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-μm CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel Charge Amplifier achieves the optical sensitivity of 19.9 V/lx ·s. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8 mV rms , and the resulting signal dynamic range is 60 dB.
Masanori Furuta - One of the best experts on this subject based on the ideXlab platform.
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A high-speed, high-sensitivity digital CMOS image sensor with a global shutter and 12-bit column-parallel cyclic A/D converters
IEEE Journal of Solid-State Circuits, 2007Co-Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji KawahitoAbstract:This paper presents a high-speed, high-sensitivity 512times512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a Charge Amplifier for high Charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-mum CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel Charge Amplifier achieves the optical sensitivity of 19.9 V/lxmiddots. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8mVrms, and the resulting signal dynamic range is 60 dB
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a high speed high sensitivity digital cmos image sensor with a global shutter and 12 bit column parallel cyclic a d converters
Symposium on VLSI Circuits, 2007Co-Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji KawahitoAbstract:This paper presents a high-speed, high-sensitivity 512x512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a Charge Amplifier for high Charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-μm CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel Charge Amplifier achieves the optical sensitivity of 19.9 V/lx ·s. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8 mV rms , and the resulting signal dynamic range is 60 dB.
Ben S. Cazzolato - One of the best experts on this subject based on the ideXlab platform.
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A digital Charge Amplifier for hysteresis elimination in piezoelectric actuators
Smart Materials and Structures, 2013Co-Authors: Mohsen Bazghaleh, Steven Grainger, Morteza Mohammadzaheri, Ben S. CazzolatoAbstract:Piezoelectric actuators are commonly used for nanopositioning due to their high resolution, low power consumption and wide operating frequency, but they suffer hysteresis, which affects linearity. In this paper, a novel digital Charge Amplifier is presented. Results show that hysteresis is reduced by 91% compared with a voltage Amplifier, but over long operational periods the digital Charge Amplifier approach suffers displacement drift. A non-linear ARX model with long-term accuracy is used with a data fusion algorithm to remove the drift. Experimental results are presented.
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ICRA - Using frequency-weighted data fusion to improve the performance of a digital Charge Amplifier
2012 IEEE International Conference on Robotics and Automation, 2012Co-Authors: Mohsen Bazghaleh, Steven Grainger, Ben S. CazzolatoAbstract:Piezoelectric actuators are the most common among a variety of smart actuators due to their high resolution, low power consumption and wide operating frequency but they suffer hysteresis which affects linearity. In this paper a novel digital Charge Amplifier is presented which reduces hysteresis and linearizes the piezoelectric actuator. A frequency-weighted data fusion algorithm uses a non-linear ARX model to remove drift and increase the bandwidth of digital Charge Amplifier. Experimental results are presented.
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Model-based drift correction of a digital Charge Amplifier
2011Co-Authors: Mohsen Bazghaleh, Steven Grainger, Ben S. CazzolatoAbstract:Piezoelectric actuators are the most common among a variety of smart actuators due to their high resolution, low power consumption and wide operating frequency but they suffer hysteresis which affects linearity. In this paper a novel digital Charge Amplifier is presented which reduces hysteresis and linearizes the piezoelectric actuator. A data fusion algorithm uses a non-linear ARX model to remove drift. Experimental results are presented.
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An innovative digital Charge Amplifier to reduce hysteresis in piezoelectric actuators
2010Co-Authors: Mohsen Bazghaleh, Steven Grainger, Ben S. CazzolatoAbstract:Smart actuators are the key components in a variety of nanopositioning applications, such as scanning probe microscopes and atomic force microscopes. Piezoelectric actuators are the most common actuators among a variety of smart actuators due to their high resolution, low power consumption and wide operating frequency but they suffer hysteresis which affects linearity. In this paper, an innovative digital Charge Amplifier is presented to reduce hysteresis in stack piezoelectric actuators. Experimental results are presented.
Yukinari Nishikawa - One of the best experts on this subject based on the ideXlab platform.
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A high-speed, high-sensitivity digital CMOS image sensor with a global shutter and 12-bit column-parallel cyclic A/D converters
IEEE Journal of Solid-State Circuits, 2007Co-Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji KawahitoAbstract:This paper presents a high-speed, high-sensitivity 512times512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a Charge Amplifier for high Charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-mum CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel Charge Amplifier achieves the optical sensitivity of 19.9 V/lxmiddots. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8mVrms, and the resulting signal dynamic range is 60 dB
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a high speed high sensitivity digital cmos image sensor with a global shutter and 12 bit column parallel cyclic a d converters
Symposium on VLSI Circuits, 2007Co-Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji KawahitoAbstract:This paper presents a high-speed, high-sensitivity 512x512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a Charge Amplifier for high Charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-μm CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel Charge Amplifier achieves the optical sensitivity of 19.9 V/lx ·s. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8 mV rms , and the resulting signal dynamic range is 60 dB.
Toru Inoue - One of the best experts on this subject based on the ideXlab platform.
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A high-speed, high-sensitivity digital CMOS image sensor with a global shutter and 12-bit column-parallel cyclic A/D converters
IEEE Journal of Solid-State Circuits, 2007Co-Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji KawahitoAbstract:This paper presents a high-speed, high-sensitivity 512times512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a Charge Amplifier for high Charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-mum CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel Charge Amplifier achieves the optical sensitivity of 19.9 V/lxmiddots. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8mVrms, and the resulting signal dynamic range is 60 dB
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a high speed high sensitivity digital cmos image sensor with a global shutter and 12 bit column parallel cyclic a d converters
Symposium on VLSI Circuits, 2007Co-Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji KawahitoAbstract:This paper presents a high-speed, high-sensitivity 512x512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a Charge Amplifier for high Charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-μm CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel Charge Amplifier achieves the optical sensitivity of 19.9 V/lx ·s. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8 mV rms , and the resulting signal dynamic range is 60 dB.