The Experts below are selected from a list of 53664 Experts worldwide ranked by ideXlab platform
David Harle - One of the best experts on this subject based on the ideXlab platform.
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Evaluation of a network on Chip Architecture based on the clockwork routed Manhattan street network using hardware emulation
48th Midwest Symposium on Circuits and Systems 2005., 2005Co-Authors: K. Oommen, David HarleAbstract:Trends in integrated circuit design indicate a shift in focus from computation to communication. Interconnect issues within devices now come to the fore as the dedicated wire and shared-bus Architectures look increasingly ill-equipped to cope with such complexity. This paper proposes a scalable network on Chip Architecture based on the Manhattan street network (MSN) using clockwork (CW) routing scheme. The proposed solution is self routing and allows for the implementation of routing functionality in hardware, eliminating the need for custom routing tables at each node. In this study, the characteristics of the proposed Architecture are evaluated based upon the first full hardware implementation of a functional MSN-CW. Due to the deterministic nature of the routing mechanism, upper bounds on network delay can be established. This makes the Architectures particularly suited to applications involving realtime constraints
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FPL - Hardware emulation of a network on Chip Architecture based on a clockwork routed manhattan street network
International Conference on Field Programmable Logic and Applications 2005., 1Co-Authors: K. Oommen, David HarleAbstract:This paper looks at hardware emulation of a network on Chip Architecture based on a clockwork routed manhattan street network
K. Oommen - One of the best experts on this subject based on the ideXlab platform.
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Evaluation of a network on Chip Architecture based on the clockwork routed Manhattan street network using hardware emulation
48th Midwest Symposium on Circuits and Systems 2005., 2005Co-Authors: K. Oommen, David HarleAbstract:Trends in integrated circuit design indicate a shift in focus from computation to communication. Interconnect issues within devices now come to the fore as the dedicated wire and shared-bus Architectures look increasingly ill-equipped to cope with such complexity. This paper proposes a scalable network on Chip Architecture based on the Manhattan street network (MSN) using clockwork (CW) routing scheme. The proposed solution is self routing and allows for the implementation of routing functionality in hardware, eliminating the need for custom routing tables at each node. In this study, the characteristics of the proposed Architecture are evaluated based upon the first full hardware implementation of a functional MSN-CW. Due to the deterministic nature of the routing mechanism, upper bounds on network delay can be established. This makes the Architectures particularly suited to applications involving realtime constraints
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FPL - Hardware emulation of a network on Chip Architecture based on a clockwork routed manhattan street network
International Conference on Field Programmable Logic and Applications 2005., 1Co-Authors: K. Oommen, David HarleAbstract:This paper looks at hardware emulation of a network on Chip Architecture based on a clockwork routed manhattan street network
Minoru Watanabe - One of the best experts on this subject based on the ideXlab platform.
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Parallel template matching operations on a dynamically reconfigurable vision-Chip Architecture
2011 IEEE 9th International New Circuits and systems conference, 2011Co-Authors: Hironari Nakada, Minoru Watanabe, Shoji KawahitoAbstract:Recently, high-speed image recognition functionality that is superior to the image recognition speed of the human eye is demanded for autonomous vehicles and robots. Currently, such embedded systems comprise a processor and memory. To recognize many images, many template images must be stored in memory and must be sent quickly from memory to the processor. For example, assuming that the system receives an external image with 1 million pixels at every 1 ms and assuming that the system must execute template-matching operations of 1 million template images with the same million pixels within 1 ms, then the transfer speed from the memory to the processor and the processor operation reaches 1 Petapixel/s. Therefore, to realize high-speed template-matching operation, a dynamically reconfigurable vision-Chip Architecture with a holographic memory and large-bandwidth optical connections has been proposed. Among such researches, this paper presents a proposal of novel parallel template-matching operations performed on the dynamically reconfigurable vision-Chip Architecture. Furthermore, the advantages of the new method are discussed based on some demonstration results.
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FPL - Dynamically Reconfigurable Vision-Chip Architecture
2010 International Conference on Field Programmable Logic and Applications, 2010Co-Authors: Maki Yasuda, Minoru WatanabeAbstract:Recently, for autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. To date, analogtype vision Chips and digital vision Chips have been developed. Nevertheless, even now, to realize such high-speed real-time image recognition operation is extremely difficult. Therefore, to realize a high-speed real-time image-recognizable vision Chip, this paper presents a proposal for a dynamically reconfigurable vision Chip Architecture. In addition, some experimental results are reported.
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Template matching operations on a dynamically reconfigurable vision-Chip Architecture
2010 10th International Symposium on Communications and Information Technologies, 2010Co-Authors: Hironari Nakada, Minoru WatanabeAbstract:Recently, for autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. To date, analog-type vision Chips and digital vision Chips have been developed. Nevertheless, even now, to realize such high-speed real-time image recognition operation is extremely difficult. Therefore, to realize a high-speed real-time image-recognizable vision Chip, this paper experimentally presents a template matching operations on a dynamically reconfigurable vision-Chip Architecture.
Paul V. Gratz - One of the best experts on this subject based on the ideXlab platform.
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WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture
ACM Transactions on Design Automation of Electronic Systems, 2014Co-Authors: Yoon Seok Yang, Reeshav Kumar, Gwan Choi, Paul V. GratzAbstract:WaveSync is a network-on-Chip Architecture for a globally asynchronous locally-synchronous (GALS) design. The WaveSync design facilitates low-latency communication leveraging the source-synchronous clock sent along with the data to time components in the datapath of a downstream router, reducing the number of synchronizations needed. WaveSync accomplishes this by partitioning the router components at each node into different clock domains, each synchronized with one of the orthogonal incoming source-synchronous clocks in a GALS 2D mesh network. The data and clock subsequently propagate through each node/router synchronously until the destination is reached, regardless of the number of hops this may take. As long as the data travels in the path of clock propagation and no congestion is encountered, it will be propagated without latching as if in a long combinatorial path, with both the clock and the data accruing delay at the same rate. The result is that the need for synchronization between the mesochronous nodes and/or the asynchronous control associated with the typical GALS network is completely eliminated. To further reduce the latency overhead of synchronization, for those occasions when synchronization is still required (when a flit takes a turn or arrives at the destination), we propose a novel less-than-one-cycle synchronizer. The proposed WaveSync network outperforms conventional GALS networks by 87--90p in average latency, synthesized using a 45nm CMOS library.
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ICCD - WaveSync: A low-latency source synchronous bypass network-on-Chip Architecture
2012 IEEE 30th International Conference on Computer Design (ICCD), 2012Co-Authors: Yoon Seok Yang, Reeshav Kumar, Gwan Choi, Paul V. GratzAbstract:WaveSync is a low-latency focused, network-on-Chip Architecture for globally-asynchronous locally-synchronous (GALS) designs. WaveSync facilitates low-latency communication leveraging the source-synchronous clock sent with the data, to time components in the downstream routers data-path to reduce the number of synchronizations needed. WaveSync accomplishes this by partitioning the router components at each node into different clock-domains, each synchronized with one of the the orthogonal incoming source synchronous clocks in a GALS 2D mesh network. The data and clock subsequently propagate through each node/router, synchronously, until the destination is reached, regardless of the number of hops it may take. As long as the data travel in the path of clock propagation, and no congestion is encountered, it will be propagated without latching, as if in a long-combinatorial path, with both the clock and the data accruing delay at the same rate. The result is that the need for synchronization between the mesochronous nodes and/or the asynchronous control associated with typical GALS network is completely eliminated. The proposed WaveSync network outperforms conventional GALS networks by 87–90% in average nanosecond latency with 1.8–6.5 times more throughput across synthetic traffic patterns and SPLASH-2 benchmark suite.
Maki Yasuda - One of the best experts on this subject based on the ideXlab platform.
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FPL - Dynamically Reconfigurable Vision-Chip Architecture
2010 International Conference on Field Programmable Logic and Applications, 2010Co-Authors: Maki Yasuda, Minoru WatanabeAbstract:Recently, for autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. To date, analogtype vision Chips and digital vision Chips have been developed. Nevertheless, even now, to realize such high-speed real-time image recognition operation is extremely difficult. Therefore, to realize a high-speed real-time image-recognizable vision Chip, this paper presents a proposal for a dynamically reconfigurable vision Chip Architecture. In addition, some experimental results are reported.