The Experts below are selected from a list of 40578 Experts worldwide ranked by ideXlab platform
Ozcan Ozturk - One of the best experts on this subject based on the ideXlab platform.
-
On-Chip Memory space partitioning for Chip multiprocessors using polyhedral algebra
Iet Computers and Digital Techniques, 2010Co-Authors: Ozcan Ozturk, Mahmut Kandemir, Mary Jane IrwinAbstract:One of the most important issues in designing a Chip multiprocessor is to decide its on-Chip Memory organisation. While it is possible to design an application-specific Memory architecture, this may not necessarily be the best option, in particular when storage demands of individual processors and/or their data sharing patterns can change from one point in execution to another for the same application. Here, two problems are formulated. First, we show how a polyhedral method can be used to design, for array-based data-intensive embedded applications, an application-specific hybrid Memory architecture that has both shared and private components. We evaluate the resulting Memory configurations using a set of benchmarks and compare them to pure private and pure shared Memory on-Chip multiprocessor architectures. The second approach proposed consider dynamic configuration of software-managed on-Chip Memory space to adapt to the runtime variations in data storage demand and interprocessor sharing patterns. The proposed framework is fully implemented using an optimising compiler, a polyhedral tool, and a Memory partitioner (based on integer linear programming), and is tested using a suite of eight data-intensive embedded applications.
-
ICPADS (1) - Multi-level on-Chip Memory hierarchy design for embedded Chip multiprocessors
12th International Conference on Parallel and Distributed Systems - (ICPADS'06), 2006Co-Authors: Ozcan Ozturk, Mahmut Kandemir, Mary Jane Irwin, Suleyman TosunAbstract:This paper proposes an integer linear programming (ILP) solution to the combined problem of Memory hierarchy design and data allocation in the context of embedded Chip multiprocessors. The proposed solution uses compiler analysis to extract data access patterns of parallel processors and employs integer linear programming for determining optimal on-Chip Memory partitioning across processors and data allocations across the resulting Memory components. Our experimental results show that the application-specific on-Chip Memory hierarchies designed using this approach are much more energy efficient than conventional (pure shared or pure private) on-Chip memories, conventional caches, and those designed by a prior work that partitions Memory space across parallel processors without designing a multi-level hierarchy.
-
CODES+ISSS - Increasing on-Chip Memory space utilization for embedded Chip multiprocessors through data compression
Proceedings of the 3rd IEEE ACM IFIP international conference on Hardware software codesign and system synthesis - CODES+ISSS '05, 2005Co-Authors: Mahmut Kandemir, Mary Jane Irwin, Ozcan OzturkAbstract:Minimizing the number of off-Chip Memory references is very important in Chip multiprocessors from both the performance and power perspectives. To achieve this the distance between successive reuses of the same data block must be reduced. However, this may not be possible in many cases due to data dependences between computations assigned to different processors. This paper focuses on software-managed on-Chip Memory space utilization for embedded Chip multiprocessors and proposes a compression-based approach to reduce the Memory space occupied by data blocks with large inter-processor reuse distances. The proposed approach has two major components: a compiler and an ILP (integer linear programming) solver. The compiler's job is to analyze the application code and extract information on data access patterns. This access pattern information is then passed to our ILP solver, which determines the data blocks to compress/decompress and the times (the program points) at which to compress/decompress them. We tested the effectiveness of this ILP based approach using access patterns extracted by our compiler from application codes. Our experimental results reveal that the proposed approach is very effective in reducing power consumption. Moreover, it leads to a lower energy consumption than an alternate scheme evaluated in our experiments for all the test cases studied.
-
CASES - Dynamic on-Chip Memory management for Chip multiprocessors
Proceedings of the 2004 international conference on Compilers architecture and synthesis for embedded systems - CASES '04, 2004Co-Authors: Mahmut Kandemir, Ozcan Ozturk, M. KarakoyAbstract:One of the most important issues in designing a Chip multiprocessor is to decide its on-Chip Memory organization. A poor on-Chip Memory design can have serious power and performance implications when running data-intensive embedded applications. While it is possible to design an application-specific Memory architecture, this may not be the best option, in particular when storage demands of individual processors and/or their data sharing patterns can change from one point in execution to another for the same application. In this paper, we consider dynamic configuration of software-managed on-Chip Memory space to adapt runtime variations in data storage demand and interprocessor sharing patterns. The proposed framework is fully implemented using an optimizing compiler, a polyhedral tool, and a Memory partitioner (based on integer linear programming), and tested using a suite of eight data-intensive embedded applications. Our experimental evaluation indicates that the proposed technique is very effective in practice and leads to much less energy consumption than all the alternate Memory management schemes tested, including one that comes up with an application-specific Memory.
-
SoCC - On-Chip Memory Management for Embedded MpSoC Architectures Based on Data Compression
2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electronics, 1Co-Authors: Ozcan Ozturk, Mahmut Kandemir, Mary Jane Irwin, Suleyman TosunAbstract:One must be very careful in utilizing the available on-Chip Memory space in embedded MpSoC architectures, which may be very challenging due to data sharing among processors. This paper proposes and evaluates an on-Chip Memory space management strategy based on data compression. The proposed strategy first uses a compiler analysis that reveals the order in which different data blocks are required by the application. After that, it builds an integer linear programming based representation of the on-Chip Memory space management problem, and solves it using a publicly-available integer linear programming tool. The solution gives the optimum order in which data blocks should be compressed and decompressed to minimize execution cycles or energy consumption under an on-Chip Memory capacity limit
Mahmut Kandemir - One of the best experts on this subject based on the ideXlab platform.
-
On-Chip Memory space partitioning for Chip multiprocessors using polyhedral algebra
Iet Computers and Digital Techniques, 2010Co-Authors: Ozcan Ozturk, Mahmut Kandemir, Mary Jane IrwinAbstract:One of the most important issues in designing a Chip multiprocessor is to decide its on-Chip Memory organisation. While it is possible to design an application-specific Memory architecture, this may not necessarily be the best option, in particular when storage demands of individual processors and/or their data sharing patterns can change from one point in execution to another for the same application. Here, two problems are formulated. First, we show how a polyhedral method can be used to design, for array-based data-intensive embedded applications, an application-specific hybrid Memory architecture that has both shared and private components. We evaluate the resulting Memory configurations using a set of benchmarks and compare them to pure private and pure shared Memory on-Chip multiprocessor architectures. The second approach proposed consider dynamic configuration of software-managed on-Chip Memory space to adapt to the runtime variations in data storage demand and interprocessor sharing patterns. The proposed framework is fully implemented using an optimising compiler, a polyhedral tool, and a Memory partitioner (based on integer linear programming), and is tested using a suite of eight data-intensive embedded applications.
-
SoCC - Exploiting large on-Chip Memory space through data recomputation
23rd IEEE International SOC Conference, 2010Co-Authors: Mahmut Kandemir, Ehat ErcanliAbstract:This paper presents a novel on-Chip Memory space utilization strategy for architectures that accommodate large on-Chip software-managed memories. In such architectures, the access latencies of data blocks are typically proportional to the distance between the processor and the requested data. Considering such an on-Chip Memory hierarchy, we propose to recompute the value of an on-Chip data, which is far from the processor, using the closer data elements instead of directly accessing the far data if it is beneficial to do so in terms of performance. This paper presents the details of a compiler algorithm that implements the proposed approach and reports the experimental data collected using six data-intensive applications programs. Our experimental evaluation indicates 8.2% performance improvement, on the average, over a state-of-the-art on-Chip Memory management strategy and shows consistent improvements for varying on-Chip Memory sizes and different data access latencies.
-
ICPADS (1) - Multi-level on-Chip Memory hierarchy design for embedded Chip multiprocessors
12th International Conference on Parallel and Distributed Systems - (ICPADS'06), 2006Co-Authors: Ozcan Ozturk, Mahmut Kandemir, Mary Jane Irwin, Suleyman TosunAbstract:This paper proposes an integer linear programming (ILP) solution to the combined problem of Memory hierarchy design and data allocation in the context of embedded Chip multiprocessors. The proposed solution uses compiler analysis to extract data access patterns of parallel processors and employs integer linear programming for determining optimal on-Chip Memory partitioning across processors and data allocations across the resulting Memory components. Our experimental results show that the application-specific on-Chip Memory hierarchies designed using this approach are much more energy efficient than conventional (pure shared or pure private) on-Chip memories, conventional caches, and those designed by a prior work that partitions Memory space across parallel processors without designing a multi-level hierarchy.
-
CODES+ISSS - Increasing on-Chip Memory space utilization for embedded Chip multiprocessors through data compression
Proceedings of the 3rd IEEE ACM IFIP international conference on Hardware software codesign and system synthesis - CODES+ISSS '05, 2005Co-Authors: Mahmut Kandemir, Mary Jane Irwin, Ozcan OzturkAbstract:Minimizing the number of off-Chip Memory references is very important in Chip multiprocessors from both the performance and power perspectives. To achieve this the distance between successive reuses of the same data block must be reduced. However, this may not be possible in many cases due to data dependences between computations assigned to different processors. This paper focuses on software-managed on-Chip Memory space utilization for embedded Chip multiprocessors and proposes a compression-based approach to reduce the Memory space occupied by data blocks with large inter-processor reuse distances. The proposed approach has two major components: a compiler and an ILP (integer linear programming) solver. The compiler's job is to analyze the application code and extract information on data access patterns. This access pattern information is then passed to our ILP solver, which determines the data blocks to compress/decompress and the times (the program points) at which to compress/decompress them. We tested the effectiveness of this ILP based approach using access patterns extracted by our compiler from application codes. Our experimental results reveal that the proposed approach is very effective in reducing power consumption. Moreover, it leads to a lower energy consumption than an alternate scheme evaluated in our experiments for all the test cases studied.
-
CASES - Dynamic on-Chip Memory management for Chip multiprocessors
Proceedings of the 2004 international conference on Compilers architecture and synthesis for embedded systems - CASES '04, 2004Co-Authors: Mahmut Kandemir, Ozcan Ozturk, M. KarakoyAbstract:One of the most important issues in designing a Chip multiprocessor is to decide its on-Chip Memory organization. A poor on-Chip Memory design can have serious power and performance implications when running data-intensive embedded applications. While it is possible to design an application-specific Memory architecture, this may not be the best option, in particular when storage demands of individual processors and/or their data sharing patterns can change from one point in execution to another for the same application. In this paper, we consider dynamic configuration of software-managed on-Chip Memory space to adapt runtime variations in data storage demand and interprocessor sharing patterns. The proposed framework is fully implemented using an optimizing compiler, a polyhedral tool, and a Memory partitioner (based on integer linear programming), and tested using a suite of eight data-intensive embedded applications. Our experimental evaluation indicates that the proposed technique is very effective in practice and leads to much less energy consumption than all the alternate Memory management schemes tested, including one that comes up with an application-specific Memory.
Naifeng Jing - One of the best experts on this subject based on the ideXlab platform.
-
IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs
IEEE Transactions on Parallel and Distributed Systems, 2018Co-Authors: Jianfei Wang, Qin Wang, Li Jiang, Xiaoyao Liang, Naifeng JingAbstract:GPGPU accelerated computing has revolutionized a broad range of applications. To serve between the ever-growing computing capability and external Memory, the on-Chip Memory is becoming increasingly important to GPGPU performance for general-purpose computing. Inherited from the traditional CPUs, however, the contemporary GPGPU on-Chip Memory design is suboptimal to the SIMT (single instruction, multiple threads) execution. In particular, the on-Chip first-level data (L1D) cache thrashing, resulting from insufficient capacity and imbalanced usage, leads to a low hit rate and limits the overall performance. In this study, we reform the contemporary on-Chip Memory design and propose an integrated and balanced on-Chip Memory (IBOM) architecture for high-performance GPGPUs. It first virtually enlarges the L1D cache size by an integrated architecture that exploits the under-utilized register file (RF) with lightweight ISA, compiler and microarchitecture supports. Then with sufficient capacity, it is able to improve the cache usage by a set balancing technique that exploits the under-utilized set resources. In our proposed IBOM design, the register and cache accesses are amenable to normal pipeline operations with simple changes. It adequately exploits the size inversion in GPGPU on-Chip Memory, and enables optimized utilization of the precious resources for higher performance and energy efficiency with even smaller on-Chip Memory size. The experiment results demonstrate that the proposed IBOM design can offer an average of 29.6 percent increase in L1D hit rate and in turn 3X performance improvement for the cache-sensitive applications.
-
MICRO - Cache-emulated register file: an integrated on-Chip Memory architecture for high performance GPGPUs
2016 49th Annual IEEE ACM International Symposium on Microarchitecture (MICRO), 2016Co-Authors: Naifeng Jing, Jianfei Wang, Li Jiang, Fengfeng Fan, Xiaoyao LiangAbstract:The on-Chip Memory design is critical to the GPGPU performance because it serves between the massive threads and the huge external Memory as a low-latency and high-throughput data communication point. However, the existing on-Chip Memory hierarchy is inherited from the conventional CPU architecture and is oftentimes sub-optimal to the SIMT (single instruction, multiple threads) execution. In this study, we surpass the traditional Memory hierarchy design and reform the on-Chip Memory into an integrated architecture with the cache-emulated register file (RF) capability tailored for high performance GPGPU computing. With the lightweight support from ISA, compiler and the modified microarchitecture, this integrated architecture can dynamically emulate a variable-sized RF and a cache in a uniform way. Evaluation results demonstrate that this novel architecture can deliver better performance and energy efficiency with smaller on-Chip Memory size. For example, it can gain an average of 50% performance improvement for the cache-sensitive applications.
Abbas Banaiyanmofrad - One of the best experts on this subject based on the ideXlab platform.
-
Resilient On-Chip Memory Design in the Nano Era
2016Co-Authors: Abbas BanaiyanmofradAbstract:Author(s): Banaiyanmofrad, Abbas | Advisor(s): Dutt, Nikil | Abstract: Aggressive technology scaling in the nano-scale regime makes Chips more susceptible to failures. This causes multiple reliability challenges in the design of modern Chips, including manufacturing defects, wear-out, and parametric variations. By increasing the number, amount, and hierarchy of on-Chip Memory blocks in emerging computing systems, the reliability of the Memory sub-system becomes an increasingly challenging design issue. The limitations of existing resilient Memory design schemes motivate us to think about new approaches considering scalability, interconnect-awareness, and cost-effectiveness as major design factors. In this thesis, we propose different approaches to address resilient on-Chip Memory design in computing systems ranging from traditional single-core processors to emerging many-core platforms. We classify our proposed approaches in five main categories: 1) Flexible and low-cost approaches to protect cache memories in single-core processors against permanent faults and transient errors, 2) Scalable fault-tolerant approaches to protect last-level caches with non-uniform cache access in Chip multiprocessors, 3) Interconnect-aware cache protection schemes in network-on-Chip architectures, 4) Relaxing Memory resiliency for approximate computing applications, and 5) System-level design space exploration, analysis, and optimization for redundancy-aware on-Chip Memory resiliency in many-core platforms. We first propose a flexible fault-tolerant cache (FFT-Cache) architecture for SRAM-based on-Chip cache memories in single-core processors working at near-threshold voltages. Then, we extend the technique proposed in FFT-Cache, to protect shared last-level cache (LLC) with Non-Uniform Cache Access (NUCA) in Chip multiprocessor (CMP) architectures, proposing REMEDIATE that leverages a flexible fault remapping technique while considering the implications of different remapping heuristics in the presence of cache banking, non-uniform latency, and interconnected network. Then, we extend REMEDIATE by introducing RESCUE with the main goal of proposing a design trend (aggressive voltage scaling + cache over-provisioning) that uses different fault remapping heuristics with salable implementation for shared multi-bank LLC in CMPs to reduce power while exploring a large design space with multiple dimensions and performing multiple sensitivity analysis. Considering multibit upsets, we propose a low-cost technique to leverage embedded erasure coding (EEC) to tackle soft errors as well as hard errors in data caches of a high-performance as well as an embedded processor. Considering non-trivial effect of interconnection fabric in Memory resiliency of network-on-Chip (NoC) platforms, we then propose a novel fault-tolerant scheme that leverages the interconnection network to protect the LLC cache banks against permanent faults. During a LLC access to a faulty area, the network detects and corrects the faults, returning the fault-free data to the requesting core. In another approach, we propose CoDEC, a Co-design approach to error coding of cache and interconnect in many-core architectures to reduce the cost of error protection compared to conventional methods. Proposing a system-wide error coding scheme, CoDEC guarantees end-to-end protection of LLC data blocks throughout the on-Chip network against errors. Observing available tradeoffs among reliability, output fidelity, performance, and energy in emerging error-resilient applications in approximate computing era motivates us to consider application-awareness in resilient Memory design. The key idea is exploiting the intrinsic tolerance of such applications to some level of errors for relaxing Memory guard-banding to reduce design overheads. As an exemplar we propose Relaxed-Cache, in which we relax the definition of faulty block depending on the number and location of faulty bits in a SRAM-based cache to save energy. In this part of thesis, we aim at cross-layer characterization and optimization of on-Chip Memory resiliency over the system stack. Our first contribution toward this approach is focusing more on scalability of Memory resiliency as a system-level design methodology for scalable fault-tolerance of distributed on-Chip memories in NoCs. We introduce a novel reliability clustering model for effective shared redundancy management toward cost-efficient fault-tolerance of on-Chip Memory blocks. Each cluster represents a group of cores that have access to shared redundancy resources for protection of their Memory blocks.
-
SRDS - Reliable On-Chip Memory Design for CMPs
2012 IEEE 31st Symposium on Reliable Distributed Systems, 2012Co-Authors: Abbas BanaiyanmofradAbstract:Aggressive technology scaling in deep sub micron regime makes Chips more susceptible to failures. This causes multiple realibility challenges in the design of modern Chips, including manufacturing defects, wear-out, and parametric variations. With increasing area occupied by different on-Chip memories in modern computing platforms such as Chip Multi-Processors (CMPs), Memory reliability becomes a challenging issue. Traditional on-Chip Memory reliability techniques (e.g., ECC) incur significant power and performance overheads. To tackle such challenges, my research introduces several designs for fault-tolerance of both L1 and L2 cache memories in uni-core processors [1], Last-level Cache (LLC) in CMPs [3][4], and LLC in Networks-on-Chip (NoCs) [2].
Jianfei Wang - One of the best experts on this subject based on the ideXlab platform.
-
IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs
IEEE Transactions on Parallel and Distributed Systems, 2018Co-Authors: Jianfei Wang, Qin Wang, Li Jiang, Xiaoyao Liang, Naifeng JingAbstract:GPGPU accelerated computing has revolutionized a broad range of applications. To serve between the ever-growing computing capability and external Memory, the on-Chip Memory is becoming increasingly important to GPGPU performance for general-purpose computing. Inherited from the traditional CPUs, however, the contemporary GPGPU on-Chip Memory design is suboptimal to the SIMT (single instruction, multiple threads) execution. In particular, the on-Chip first-level data (L1D) cache thrashing, resulting from insufficient capacity and imbalanced usage, leads to a low hit rate and limits the overall performance. In this study, we reform the contemporary on-Chip Memory design and propose an integrated and balanced on-Chip Memory (IBOM) architecture for high-performance GPGPUs. It first virtually enlarges the L1D cache size by an integrated architecture that exploits the under-utilized register file (RF) with lightweight ISA, compiler and microarchitecture supports. Then with sufficient capacity, it is able to improve the cache usage by a set balancing technique that exploits the under-utilized set resources. In our proposed IBOM design, the register and cache accesses are amenable to normal pipeline operations with simple changes. It adequately exploits the size inversion in GPGPU on-Chip Memory, and enables optimized utilization of the precious resources for higher performance and energy efficiency with even smaller on-Chip Memory size. The experiment results demonstrate that the proposed IBOM design can offer an average of 29.6 percent increase in L1D hit rate and in turn 3X performance improvement for the cache-sensitive applications.
-
MICRO - Cache-emulated register file: an integrated on-Chip Memory architecture for high performance GPGPUs
2016 49th Annual IEEE ACM International Symposium on Microarchitecture (MICRO), 2016Co-Authors: Naifeng Jing, Jianfei Wang, Li Jiang, Fengfeng Fan, Xiaoyao LiangAbstract:The on-Chip Memory design is critical to the GPGPU performance because it serves between the massive threads and the huge external Memory as a low-latency and high-throughput data communication point. However, the existing on-Chip Memory hierarchy is inherited from the conventional CPU architecture and is oftentimes sub-optimal to the SIMT (single instruction, multiple threads) execution. In this study, we surpass the traditional Memory hierarchy design and reform the on-Chip Memory into an integrated architecture with the cache-emulated register file (RF) capability tailored for high performance GPGPU computing. With the lightweight support from ISA, compiler and the modified microarchitecture, this integrated architecture can dynamically emulate a variable-sized RF and a cache in a uniform way. Evaluation results demonstrate that this novel architecture can deliver better performance and energy efficiency with smaller on-Chip Memory size. For example, it can gain an average of 50% performance improvement for the cache-sensitive applications.