The Experts below are selected from a list of 11943 Experts worldwide ranked by ideXlab platform
Lin Zhong - One of the best experts on this subject based on the ideXlab platform.
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User-perceived latency driven Voltage Scaling for interactive applications
Proceedings. 42nd Design Automation Conference 2005., 2005Co-Authors: Lin ZhongAbstract:Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level Voltage Scaling techniques, such as dynamic Voltage Scaling (DVS) and adaptive body biasing (ABB), have been shown to reduce energy consumption effectively. Previous works on DVS and ABB exploit low CPU utilization of the processor to drive Voltage Scaling. This has become inadequate for modern interactive applications involving high CPU usage. In this work, we target computer responsiveness during Voltage Scaling to exploit more opportunities for energy reduction. Instead of CPU utilization, we use the user-perceived latency, the delay between user input and computer response, to drive Voltage Scaling. Considering the tradeoff between energy consumption and computer responsiveness during Voltage Scaling not only reduces energy consumption effectively, but also ensures good computer responsiveness for interactive applications. Experimental results show that for the 70nm technology, during the execution of seven commonly-used interactive applications, the energy consumption of the processor using user-perceived latency driven DVS is reduced by an average of 37.3%, and the user-perceived latency by an average of 18.3%, compared to CPU utilization driven DVS. If both DVS and ABB are performed simultaneously based on the user-perceived latency, then the energy consumption is reduced by another 38.9% compared to when DVS is performed alone, while maintaining a similar computer responsiveness level. We have implemented user-perceived latency driven Voltage Scaling under Linux with X Window system. However, the methodology is extensible to other operating systems as well.
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DAC - User-perceived latency driven Voltage Scaling for interactive applications
Proceedings of the 42nd annual conference on Design automation - DAC '05, 2005Co-Authors: Lin ZhongAbstract:Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level Voltage Scaling techniques, such as dynamic Voltage Scaling (DVS) and adaptive body biasing (ABB), have been shown to reduce energy consumption effectively. Previous works on DVS and ABB exploit low CPU utilization of the processor to drive Voltage Scaling. This has become inadequate for modern interactive applications involving high CPU usage. In this work, we target computer responsiveness during Voltage Scaling to exploit more opportunities for energy reduction. Instead of CPU utilization, we use the user-perceived latency, the delay between user input and computer response, to drive Voltage Scaling. Considering the tradeoff between energy consumption and computer responsiveness during Voltage Scaling not only reduces energy consumption effectively, but also ensures good computer responsiveness for interactive applications. Experimental results show that for the 70nm technology, during the execution of seven commonly-used interactive applications, the energy consumption of the processor using user-perceived latency driven DVS is reduced by an average of 37.3%, and the user-perceived latency by an average of 18.3%, compared to CPU utilization driven DVS. If both DVS and ABB are performed simultaneously based on the user-perceived latency, then the energy consumption is reduced by another 38.9% compared to when DVS is performed alone, while maintaining a similar computer responsiveness level. We have implemented user-perceived latency driven Voltage Scaling under Linux with X Window system. However, the methodology is extensible to other operating systems as well.
Robert W. Brodersen - One of the best experts on this subject based on the ideXlab platform.
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Threshold Voltage Scaling and Control
Low-Power CMOS Design, 2020Co-Authors: Anantha P. Chandrakasan, Robert W. BrodersenAbstract:This chapter contains sections titled: Ion-Implanted Complementary MOS Transistors in Low-Voltage Circuits Trading Speed for Low Power by Choice of Supply and Threshold Voltages Limitation of CMOS Supply-Voltage Scaling by MOSFET Threshold-Voltage Variation ]]>
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design issues for dynamic Voltage Scaling
International Symposium on Low Power Electronics and Design, 2000Co-Authors: Thomas D Burd, Robert W. BrodersenAbstract:Processors in portable electronic devices generally have a computational load which has time-varying performance requirements. Dynamic Voltage Scaling is a method to vary the processor's supply Voltage so that it consumes the minimal amount of energy by operating at the minimum performance level required by the active software processes. A dynamically varying supply Voltage has implications on the processor circuit design and design flow, but with some minimal constraints it is straightforward to design a processor with this capability.
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ISLPED - Design issues for dynamic Voltage Scaling
Proceedings of the 2000 international symposium on Low power electronics and design - ISLPED '00, 2000Co-Authors: Thomas D Burd, Robert W. BrodersenAbstract:Processors in portable electronic devices generally have a computational load which has time-varying performance requirements. Dynamic Voltage Scaling is a method to vary the processor's supply Voltage so that it consumes the minimal amount of energy by operating at the minimum performance level required by the active software processes. A dynamically varying supply Voltage has implications on the processor circuit design and design flow, but with some minimal constraints it is straightforward to design a processor with this capability.
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the simulation and evaluation of dynamic Voltage Scaling algorithms
International Symposium on Low Power Electronics and Design, 1998Co-Authors: Trevor Pering, Thomas D Burd, Robert W. BrodersenAbstract:The reduction of energy consumption in microprocessors can be accomplished without impacting the peak performance through the use of dynamic Voltage Scaling (DVS). This approach varies the processor Voltage under software control to meet dynamically varying performance requirements. This paper presents a foundation for the simulation and analysis of DVS algorithms. These algorithms are applied to a benchmark suite specifically targeted for PDA devices.
B.m. Al Hashimi - One of the best experts on this subject based on the ideXlab platform.
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Quasi-static Voltage Scaling for energy minimization with time constraints
Design Automation and Test in Europe, 2005Co-Authors: A. Andrei, M.t. Schmitz, P. Eles, Z. Peng, B.m. Al HashimiAbstract:Supply Voltage Scaling and adaptive body-biasing are important techniques that help to reduce the energy dissipation of embedded systems. This is achieved by dynamically adjusting the Voltage and performance settings according to the application needs. In order to take full advantage of slack that arises from variations in the execution time, it is important to recalculate the Voltage (performance) settings during run time, i.e., online. However Voltage Scaling (VS) is computationally expensive, and thus significantly hampers the possible energy savings. To overcome the online complexity, we propose a quasi-static Voltage Scaling scheme, with a constant online time complexity O(1). This allows us to increase the exploitable slack as well as to avoid the energy dissipated due to online recalculation of the Voltage settings. We conduct several experiments that demonstrate the advantages of the proposed technique over the previously published Voltage Scaling approaches.
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DATE - Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
Design Automation and Test in Europe, 2005Co-Authors: A. Andrei, M.t. Schmitz, P. Eles, Z. Peng, B.m. Al HashimiAbstract:Supply Voltage Scaling and adaptive body-biasing are important techniques that help to reduce the energy dissipation of embedded systems. This is achieved by dynamically adjusting the Voltage and performance settings according to the application needs. In order to take full advantage of slack that arises from variations in the execution time, it is important to recalculate the Voltage (performance) settings during run time, i.e., online. However Voltage Scaling (VS) is computationally expensive, and thus significantly hampers the possible energy savings. To overcome the online complexity, we propose a quasi-static Voltage Scaling scheme, with a constant online time complexity O(1). This allows us to increase the exploitable slack as well as to avoid the energy dissipated due to online recalculation of the Voltage settings. We conduct several experiments that demonstrate the advantages of the proposed technique over the previously published Voltage Scaling approaches.
A. Andrei - One of the best experts on this subject based on the ideXlab platform.
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Quasi-Static Voltage Scaling for Energy Minimization With Time Constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011Co-Authors: A. Andrei, P. Eles, Olivera Jovanovic, Marcus Schmitz, Jens Ogniewski, Z. PengAbstract:Supply Voltage Scaling and adaptive body biasing (ABB) are important techniques that help to reduce the energy dissipation of embedded systems. This is achieved by dynamically adjusting the Voltage and performance settings according to the application needs. In order to take full advantage of slack that arises from variations in the execution time, it is important to recalculate the Voltage (performance) settings during runtime, i.e., online. However, optimal Voltage Scaling algorithms are computationally expensive, and thus, if used online, significantly hamper the possible energy savings. To overcome the online complexity, we propose a quasi-static Voltage Scaling (QSVS) scheme, with a constant online time complexity O(1). This allows to increase the exploitable slack as well as to avoid the energy dissipated due to online recalculation of the Voltage settings.
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Quasi-static Voltage Scaling for energy minimization with time constraints
Design Automation and Test in Europe, 2005Co-Authors: A. Andrei, M.t. Schmitz, P. Eles, Z. Peng, B.m. Al HashimiAbstract:Supply Voltage Scaling and adaptive body-biasing are important techniques that help to reduce the energy dissipation of embedded systems. This is achieved by dynamically adjusting the Voltage and performance settings according to the application needs. In order to take full advantage of slack that arises from variations in the execution time, it is important to recalculate the Voltage (performance) settings during run time, i.e., online. However Voltage Scaling (VS) is computationally expensive, and thus significantly hampers the possible energy savings. To overcome the online complexity, we propose a quasi-static Voltage Scaling scheme, with a constant online time complexity O(1). This allows us to increase the exploitable slack as well as to avoid the energy dissipated due to online recalculation of the Voltage settings. We conduct several experiments that demonstrate the advantages of the proposed technique over the previously published Voltage Scaling approaches.
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DATE - Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
Design Automation and Test in Europe, 2005Co-Authors: A. Andrei, M.t. Schmitz, P. Eles, Z. Peng, B.m. Al HashimiAbstract:Supply Voltage Scaling and adaptive body-biasing are important techniques that help to reduce the energy dissipation of embedded systems. This is achieved by dynamically adjusting the Voltage and performance settings according to the application needs. In order to take full advantage of slack that arises from variations in the execution time, it is important to recalculate the Voltage (performance) settings during run time, i.e., online. However Voltage Scaling (VS) is computationally expensive, and thus significantly hampers the possible energy savings. To overcome the online complexity, we propose a quasi-static Voltage Scaling scheme, with a constant online time complexity O(1). This allows us to increase the exploitable slack as well as to avoid the energy dissipated due to online recalculation of the Voltage settings. We conduct several experiments that demonstrate the advantages of the proposed technique over the previously published Voltage Scaling approaches.
R. Reis - One of the best experts on this subject based on the ideXlab platform.
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Impact of dynamic Voltage Scaling and thermal factors on SRAM reliability
Microelectronics Reliability, 2020Co-Authors: F. R. Rosa, Gilson Wirth, Raphael Martins Brum, Fernanda Lima Kastensmidt, R. ReisAbstract:This work investigates the effects of temperature and Voltage Scaling in neutron-induced bit-flip in SRAM memory cells. Proposed approach allows determining the critical charge according to the dynamic behavior of the temperature as a function of the Voltage Scaling. Experimental results show that both temperature and Voltage Scaling can increase in at least two times the susceptibility of SRAM cells to soft error rate (SER). In addition, a model for electrical simulation for soft error and different Voltages was described to investigate the effects observed in the practical neutron irradiation experiments. Results can guide designers to predict soft error effects during the lifetime of SRAM-based devices considering different power supply modes.Peer-reviewedPost-print26th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Toulouse, France
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ICECS - Impact of dynamic Voltage Scaling and thermal factors on FinFET-based SRAM reliability
2015 IEEE International Conference on Electronics Circuits and Systems (ICECS), 2015Co-Authors: F. R. Rosa, Raphael Martins Brum, Gilson I. Wirth, R. ReisAbstract:FinFET technology appears as an alternative solution to mitigate short-channel effects in traditional CMOS down-scaled technology. Emerging embedded systems are likely to employ FinFET and dynamic Voltage Scaling (DVS), aiming to improve system performance and energy-efficiency. This paper claims that the use of DVS increases the susceptibility of FinFET-based SRAM cells to soft errors under radiation effects. To investigate that, a methodology that allows determining the critical charge according to the dynamic behaviour of the temperature as a function of the Voltage Scaling is used. Obtained results support our claim by showing that both temperature and Voltage Scaling can increase up to five times the susceptibility of FinFET-based SRAM cells to the occurrence of soft errors.
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Impact of dynamic Voltage Scaling and thermal factors on SRAM reliability
Microelectronics Reliability, 2015Co-Authors: Felipe Rosa, Raphael Martins Brum, Gilson I. Wirth, Fernanda Lima Kastensmidt, R. ReisAbstract:Abstract This work investigates the effects of temperature and Voltage Scaling in neutron-induced bit-flip in SRAM memory cells. Proposed approach allows determining the critical charge according to the dynamic behavior of the temperature as a function of the Voltage Scaling. Experimental results show that both temperature and Voltage Scaling can increase in at least two times the susceptibility of SRAM cells to soft error rate (SER). In addition, a model for electrical simulation for soft error and different Voltages was described to investigate the effects observed in the practical neutron irradiation experiments. Results can guide designers to predict soft error effects during the lifetime of SRAM-based devices considering different power supply modes.
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Impact of dynamic Voltage Scaling and thermal factors on FinFET-based SRAM reliability
2015 IEEE International Conference on Electronics Circuits and Systems (ICECS), 2015Co-Authors: F. R. Rosa, Gilson Wirth, Raphael Martins Brum, R. ReisAbstract:FinFET technology appears as an alternative solution to mitigate short-channel effects in traditional CMOS down-scaled technology. Emerging embedded systems are likely to employ FinFET and dynamic Voltage Scaling (DVS), aiming to improve system performance and energy-efficiency. This paper claims that the use of DVS increases the susceptibility of FinFET-based SRAM cells to soft errors under radiation effects. To investigate that, a methodology that allows determining the critical charge according to the dynamic behaviour of the temperature as a function of the Voltage Scaling is used. Obtained results support our claim by showing that both temperature and Voltage Scaling can increase up to five times the susceptibility of FinFET-based SRAM cells to the occurrence of soft errors.
