The Experts below are selected from a list of 165 Experts worldwide ranked by ideXlab platform
Prabal Dutta - One of the best experts on this subject based on the ideXlab platform.
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MBus: A System Integration Bus for the Modular Microscale Computing Class
IEEE Micro, 2016Co-Authors: Pat Pannuto, Yoonmyung Lee, Ye-sheng Kuo, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, Prabal DuttaAbstract:I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized--yet reusable--components with an interconnect that permits tiny, ultra-low-power systems. In contrast to today's interconnects, which are limited by power-hungry pull-ups or high-overhead Chip Select lines, the authors' approach operates at lower power, with a fixed pin count, using fully synthesizable logic, and with surprisingly low-protocol overhead. The authors present MBus, a new four-pin, 22.6 pJ/bit/Chip Chip-to-Chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low-power system operation by automatically power gating each Chip in the system, easing the integration of active and inactive circuits. In addition, they introduce power-oblivious communication, which guarantees message reception even if the recipient is inactive. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that draw nanowatts.
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ISCA - MBus: an ultra-low power interconnect bus for next generation nanopower systems
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015Co-Authors: Pat Pannuto, Yoonmyung Lee, Ye-sheng Kuo, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, Prabal DuttaAbstract:As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized---yet reusable---components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead Chip-Select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/Chip Chip-to-Chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each Chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom Chips from three different semiconductor processes. A three-Chip, 2.2mm3 MBus system draws 8nW of total system standby power and uses only 22.6 pJ/bit/Chip for communication. This is the lowest power for any system bus with MBus's feature set.
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MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems.
Proceedings. International Symposium on Computer Architecture, 2015Co-Authors: Pat Pannuto, Yoonmyung Lee, Ye-sheng Kuo, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, Prabal DuttaAbstract:As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead Chip-Select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/Chip Chip-to-Chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each Chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom Chips from three different semiconductor processes. A three-Chip, 2.2 mm3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/Chip for communication. This is the lowest power for any system bus with MBus's feature set.
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mbus a 17 5 pj bit Chip portable interconnect bus for millimeter scale sensor systems with 8 nw standby power
Custom Integrated Circuits Conference, 2014Co-Authors: Ye-sheng Kuo, Pat Pannuto, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, David Blaauw, Prabal Dutta, Inhee Lee, Yoonmyung LeeAbstract:We propose an ultra-low power interconnect bus for millimeter-scale wireless sensor nodes. Using only 4 IO pads, the bus minimizes the required Chip real estate, enabling ultrasmall form factors in modular sensor node designs. Low power is achieved using a “clockless” design of member nodes while aggressive power gating allows an ultra-low power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with PMUs that have a special low power standby mode. The MBus is fully synthesizable and uses robust timing. Implemented in a 3 module system in 180nm technology, Mbus achieves 8nW of standby power and 17.5 pJ/bit/Chip. Index Terms — Wireless sensor nodes, sensor systems, data buses, interconnections. INTRODUCTION Continued advances in ultra-low power circuit techniques have steadily moved the next generation of computer systems towards the vision of “smart dust” – a miniature, integrated sensing, computing, storage, and communication platform [1]. These systems are highly optimized in volume and power draw, targeting a mm3 form factor and running on single digit μW in active mode and nW in standby mode [2]. Early efforts [1][3] to realize such systems have resulted in monolithic and tightly integrated designs, with little capability for reuse. This design approach is in contrast to the modularity that has characterized embedded systems design and enabled it to address a highly diverse application space. The miniature sensor node application space is similarly diverse, ranging from implantable medical monitors to nearly invisible surveillance, to infrastructure monitoring. Hence, a modular design approach that enables extensive reuse of Chip modules is key to fully address its application space. A critical component in a modular platform is the bus through which the different modules communicate with each other. However, existing bus standards do not address the unique constraints of millimeter-scale sensor systems. We will show that the number of wires required in SPI [4] make it difficult to meet the millimeter size constraint while the power consumption of I2C [5] is orders of magnitude higher than the allowed power budget. Recently, a low power variant of I2C [6] was proposed for a modular millimeter sensor node, shown in Fig. 1, right. The system consists of several stacked Chip layers, each performing a key function (e.g, processor, memory, sensor interface, radio, etc.). However, the proposed bus requires careful matching of timing between nodes reducing robustness as well as requiring custom design, limiting portability. To address the unique constraints of millimeter-scale sensor nodes, we propose a new Chip-to-Chip bus interconnect, referred to as MBus, that is as conservative with resources as the modules it connects. MBus nodes are arranged in a ring topology, support multi-master communication, and use highly robust, fully synthesizable signaling. MBus uses only 4 IO pads, provides predictable latency, and features a novel, robust reset mechanism. To address the extreme low power constraints, member nodes in MBus are “clockless”. Also, all but 53 gates are power gated in standby mode while still enabling any node to wake up the entire system and switch the Power Management Unit (PMU) to active power mode. We present silicon measurements of a 3 layer sensor system implemented in 180 nm technology and achieve >10Mb/s data rate, with 17.55 pJ/bit/Chip and 8 nW standby power. SYSTEM INTERCONNECT DESIGN REQUIREMENTS In this section, we introduce the key design requirements for supporting ultra space-constrained systems and why this poses a unique challenge requiring a new bus interface. Low, fixed wire count per node. The target systems are highly space-constrained and even state-of-the-art wire bonding techniques require at least 35~65 μm/pad. When accounting for several power supply voltages and a few module-specific IOs, only a handful of pads remain for the bus interface in a 1 mm form factor. This makes the use of serial buses, such as SPI [4], difficult since they require a dedicated Chip-Select line for each component in the system. Hence, the maximum number of components needs to be anticipated ahead of time, often resulting in over-provisioning and a large total pad area. For instance, in a moderate 10 node system, the SPI controller would require at least 14 bus pads, which is impossible to realize in a millimeter-scale system. Low active power. A viable interface cannot dominate the μW power budget of millimeter sensors. This eliminates any pad-efficient open drain-based designs that allow biFigure 1. 1cc computer [3] (left) and a 2.2×1.1×0.8 mm stacked miniature wireless sensor node [6] (right). directional wires, due to high active power. For instance, I2C [5] requires only 4 pads per module, but uses a kΩ-range pull-up resistor resulting in 100’s of μW of power draw, which is 100× the typical power budget of a millimeter-scale sensor node. Standby power management. In standby mode, power consumption must be reduced to the nW range to enable long lifetimes with millimeter batteries and perpetual operation with harvesting. This requires aggressive power gating and a PMU that can switch to an ultra-low, nW power mode. To avoid additional wires for communicating wakeup events, the bus interface must support a wakeup request originating from any node. This poses two challenges: 1) The logic that monitors/transmits such an event must be minimized since it remains always active and directly contributes to the standby power; 2) When the wakeup request is transmitted in the bus, the PMU is still in standby mode, meaning that active current draw used for this transmission cannot exceed the nA range. Fully synthesizable. Use of custom designed components significantly increases time and effort to migrate between technologies and impedes adoption. For example, the I2C variant in [6] used custom drivers, ratioed logic, and delay chains that require post-silicon tuning. A synthesizable bus interface not only allows fast design by “dropping-in” fully verified Verilog, it also ensures robust timing which is automatically checked by tools. However, disallowing more complex circuit structures increases the challenges to meet the low wire-count and power draw requirements. Systems Constraints. Finally, to be a viable system bus, MBus must provide multi-master operation, a robust reset mechanism, and dataand device-independent behavior. DESIGN & IMPLEMENTATION Each MBus node has four signals: DOUT, DIN, CLKOUT, and CLKIN. MBus nodes are arranged in ring topology, as shown in Fig. 2, connecting DOUT/CLKOUT to the next node’s DIN/CLKIN and eventually looping back. Signals “shootthrough”, and nodes have no local clock. One node must be a MBus mediator module. The mediator is responsible for generating the bus clock and mediating arbitration. While the bus is idle, regular nodes forward both DATA and CLK. The mediator breaks the loop by fixing both CLKOUT and DOUT high in idle/standby mode. To provide a robust, reliable inband, data-independent reset, MBus nodes feature a separate Interrupt Detector block that identifies an MBus Interrupt: At least three edges on DATA with no CLK edges. Fig. 3 shows the functional diagram of a single MBus node.
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CICC - MBus: A 17.5 pJ/bit/Chip portable interconnect bus for millimeter-scale sensor systems with 8 nW standby power
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014Co-Authors: Ye-sheng Kuo, Pat Pannuto, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, David Blaauw, Prabal Dutta, Inhee Lee, Yoonmyung LeeAbstract:We propose an ultra-low power interconnect bus for millimeter-scale wireless sensor nodes. Using only 4 IO pads, the bus minimizes the required Chip real estate, enabling ultrasmall form factors in modular sensor node designs. Low power is achieved using a “clockless” design of member nodes while aggressive power gating allows an ultra-low power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with PMUs that have a special low power standby mode. The MBus is fully synthesizable and uses robust timing. Implemented in a 3 module system in 180nm technology, Mbus achieves 8nW of standby power and 17.5 pJ/bit/Chip. Index Terms — Wireless sensor nodes, sensor systems, data buses, interconnections. INTRODUCTION Continued advances in ultra-low power circuit techniques have steadily moved the next generation of computer systems towards the vision of “smart dust” – a miniature, integrated sensing, computing, storage, and communication platform [1]. These systems are highly optimized in volume and power draw, targeting a mm3 form factor and running on single digit μW in active mode and nW in standby mode [2]. Early efforts [1][3] to realize such systems have resulted in monolithic and tightly integrated designs, with little capability for reuse. This design approach is in contrast to the modularity that has characterized embedded systems design and enabled it to address a highly diverse application space. The miniature sensor node application space is similarly diverse, ranging from implantable medical monitors to nearly invisible surveillance, to infrastructure monitoring. Hence, a modular design approach that enables extensive reuse of Chip modules is key to fully address its application space. A critical component in a modular platform is the bus through which the different modules communicate with each other. However, existing bus standards do not address the unique constraints of millimeter-scale sensor systems. We will show that the number of wires required in SPI [4] make it difficult to meet the millimeter size constraint while the power consumption of I2C [5] is orders of magnitude higher than the allowed power budget. Recently, a low power variant of I2C [6] was proposed for a modular millimeter sensor node, shown in Fig. 1, right. The system consists of several stacked Chip layers, each performing a key function (e.g, processor, memory, sensor interface, radio, etc.). However, the proposed bus requires careful matching of timing between nodes reducing robustness as well as requiring custom design, limiting portability. To address the unique constraints of millimeter-scale sensor nodes, we propose a new Chip-to-Chip bus interconnect, referred to as MBus, that is as conservative with resources as the modules it connects. MBus nodes are arranged in a ring topology, support multi-master communication, and use highly robust, fully synthesizable signaling. MBus uses only 4 IO pads, provides predictable latency, and features a novel, robust reset mechanism. To address the extreme low power constraints, member nodes in MBus are “clockless”. Also, all but 53 gates are power gated in standby mode while still enabling any node to wake up the entire system and switch the Power Management Unit (PMU) to active power mode. We present silicon measurements of a 3 layer sensor system implemented in 180 nm technology and achieve >10Mb/s data rate, with 17.55 pJ/bit/Chip and 8 nW standby power. SYSTEM INTERCONNECT DESIGN REQUIREMENTS In this section, we introduce the key design requirements for supporting ultra space-constrained systems and why this poses a unique challenge requiring a new bus interface. Low, fixed wire count per node. The target systems are highly space-constrained and even state-of-the-art wire bonding techniques require at least 35~65 μm/pad. When accounting for several power supply voltages and a few module-specific IOs, only a handful of pads remain for the bus interface in a 1 mm form factor. This makes the use of serial buses, such as SPI [4], difficult since they require a dedicated Chip-Select line for each component in the system. Hence, the maximum number of components needs to be anticipated ahead of time, often resulting in over-provisioning and a large total pad area. For instance, in a moderate 10 node system, the SPI controller would require at least 14 bus pads, which is impossible to realize in a millimeter-scale system. Low active power. A viable interface cannot dominate the μW power budget of millimeter sensors. This eliminates any pad-efficient open drain-based designs that allow biFigure 1. 1cc computer [3] (left) and a 2.2×1.1×0.8 mm stacked miniature wireless sensor node [6] (right). directional wires, due to high active power. For instance, I2C [5] requires only 4 pads per module, but uses a kΩ-range pull-up resistor resulting in 100’s of μW of power draw, which is 100× the typical power budget of a millimeter-scale sensor node. Standby power management. In standby mode, power consumption must be reduced to the nW range to enable long lifetimes with millimeter batteries and perpetual operation with harvesting. This requires aggressive power gating and a PMU that can switch to an ultra-low, nW power mode. To avoid additional wires for communicating wakeup events, the bus interface must support a wakeup request originating from any node. This poses two challenges: 1) The logic that monitors/transmits such an event must be minimized since it remains always active and directly contributes to the standby power; 2) When the wakeup request is transmitted in the bus, the PMU is still in standby mode, meaning that active current draw used for this transmission cannot exceed the nA range. Fully synthesizable. Use of custom designed components significantly increases time and effort to migrate between technologies and impedes adoption. For example, the I2C variant in [6] used custom drivers, ratioed logic, and delay chains that require post-silicon tuning. A synthesizable bus interface not only allows fast design by “dropping-in” fully verified Verilog, it also ensures robust timing which is automatically checked by tools. However, disallowing more complex circuit structures increases the challenges to meet the low wire-count and power draw requirements. Systems Constraints. Finally, to be a viable system bus, MBus must provide multi-master operation, a robust reset mechanism, and dataand device-independent behavior. DESIGN & IMPLEMENTATION Each MBus node has four signals: DOUT, DIN, CLKOUT, and CLKIN. MBus nodes are arranged in ring topology, as shown in Fig. 2, connecting DOUT/CLKOUT to the next node’s DIN/CLKIN and eventually looping back. Signals “shootthrough”, and nodes have no local clock. One node must be a MBus mediator module. The mediator is responsible for generating the bus clock and mediating arbitration. While the bus is idle, regular nodes forward both DATA and CLK. The mediator breaks the loop by fixing both CLKOUT and DOUT high in idle/standby mode. To provide a robust, reliable inband, data-independent reset, MBus nodes feature a separate Interrupt Detector block that identifies an MBus Interrupt: At least three edges on DATA with no CLK edges. Fig. 3 shows the functional diagram of a single MBus node.
Pat Pannuto - One of the best experts on this subject based on the ideXlab platform.
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MBus: A System Integration Bus for the Modular Microscale Computing Class
IEEE Micro, 2016Co-Authors: Pat Pannuto, Yoonmyung Lee, Ye-sheng Kuo, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, Prabal DuttaAbstract:I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized--yet reusable--components with an interconnect that permits tiny, ultra-low-power systems. In contrast to today's interconnects, which are limited by power-hungry pull-ups or high-overhead Chip Select lines, the authors' approach operates at lower power, with a fixed pin count, using fully synthesizable logic, and with surprisingly low-protocol overhead. The authors present MBus, a new four-pin, 22.6 pJ/bit/Chip Chip-to-Chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low-power system operation by automatically power gating each Chip in the system, easing the integration of active and inactive circuits. In addition, they introduce power-oblivious communication, which guarantees message reception even if the recipient is inactive. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that draw nanowatts.
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ISCA - MBus: an ultra-low power interconnect bus for next generation nanopower systems
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015Co-Authors: Pat Pannuto, Yoonmyung Lee, Ye-sheng Kuo, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, Prabal DuttaAbstract:As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized---yet reusable---components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead Chip-Select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/Chip Chip-to-Chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each Chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom Chips from three different semiconductor processes. A three-Chip, 2.2mm3 MBus system draws 8nW of total system standby power and uses only 22.6 pJ/bit/Chip for communication. This is the lowest power for any system bus with MBus's feature set.
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MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems.
Proceedings. International Symposium on Computer Architecture, 2015Co-Authors: Pat Pannuto, Yoonmyung Lee, Ye-sheng Kuo, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, Prabal DuttaAbstract:As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead Chip-Select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/Chip Chip-to-Chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each Chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom Chips from three different semiconductor processes. A three-Chip, 2.2 mm3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/Chip for communication. This is the lowest power for any system bus with MBus's feature set.
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mbus a 17 5 pj bit Chip portable interconnect bus for millimeter scale sensor systems with 8 nw standby power
Custom Integrated Circuits Conference, 2014Co-Authors: Ye-sheng Kuo, Pat Pannuto, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, David Blaauw, Prabal Dutta, Inhee Lee, Yoonmyung LeeAbstract:We propose an ultra-low power interconnect bus for millimeter-scale wireless sensor nodes. Using only 4 IO pads, the bus minimizes the required Chip real estate, enabling ultrasmall form factors in modular sensor node designs. Low power is achieved using a “clockless” design of member nodes while aggressive power gating allows an ultra-low power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with PMUs that have a special low power standby mode. The MBus is fully synthesizable and uses robust timing. Implemented in a 3 module system in 180nm technology, Mbus achieves 8nW of standby power and 17.5 pJ/bit/Chip. Index Terms — Wireless sensor nodes, sensor systems, data buses, interconnections. INTRODUCTION Continued advances in ultra-low power circuit techniques have steadily moved the next generation of computer systems towards the vision of “smart dust” – a miniature, integrated sensing, computing, storage, and communication platform [1]. These systems are highly optimized in volume and power draw, targeting a mm3 form factor and running on single digit μW in active mode and nW in standby mode [2]. Early efforts [1][3] to realize such systems have resulted in monolithic and tightly integrated designs, with little capability for reuse. This design approach is in contrast to the modularity that has characterized embedded systems design and enabled it to address a highly diverse application space. The miniature sensor node application space is similarly diverse, ranging from implantable medical monitors to nearly invisible surveillance, to infrastructure monitoring. Hence, a modular design approach that enables extensive reuse of Chip modules is key to fully address its application space. A critical component in a modular platform is the bus through which the different modules communicate with each other. However, existing bus standards do not address the unique constraints of millimeter-scale sensor systems. We will show that the number of wires required in SPI [4] make it difficult to meet the millimeter size constraint while the power consumption of I2C [5] is orders of magnitude higher than the allowed power budget. Recently, a low power variant of I2C [6] was proposed for a modular millimeter sensor node, shown in Fig. 1, right. The system consists of several stacked Chip layers, each performing a key function (e.g, processor, memory, sensor interface, radio, etc.). However, the proposed bus requires careful matching of timing between nodes reducing robustness as well as requiring custom design, limiting portability. To address the unique constraints of millimeter-scale sensor nodes, we propose a new Chip-to-Chip bus interconnect, referred to as MBus, that is as conservative with resources as the modules it connects. MBus nodes are arranged in a ring topology, support multi-master communication, and use highly robust, fully synthesizable signaling. MBus uses only 4 IO pads, provides predictable latency, and features a novel, robust reset mechanism. To address the extreme low power constraints, member nodes in MBus are “clockless”. Also, all but 53 gates are power gated in standby mode while still enabling any node to wake up the entire system and switch the Power Management Unit (PMU) to active power mode. We present silicon measurements of a 3 layer sensor system implemented in 180 nm technology and achieve >10Mb/s data rate, with 17.55 pJ/bit/Chip and 8 nW standby power. SYSTEM INTERCONNECT DESIGN REQUIREMENTS In this section, we introduce the key design requirements for supporting ultra space-constrained systems and why this poses a unique challenge requiring a new bus interface. Low, fixed wire count per node. The target systems are highly space-constrained and even state-of-the-art wire bonding techniques require at least 35~65 μm/pad. When accounting for several power supply voltages and a few module-specific IOs, only a handful of pads remain for the bus interface in a 1 mm form factor. This makes the use of serial buses, such as SPI [4], difficult since they require a dedicated Chip-Select line for each component in the system. Hence, the maximum number of components needs to be anticipated ahead of time, often resulting in over-provisioning and a large total pad area. For instance, in a moderate 10 node system, the SPI controller would require at least 14 bus pads, which is impossible to realize in a millimeter-scale system. Low active power. A viable interface cannot dominate the μW power budget of millimeter sensors. This eliminates any pad-efficient open drain-based designs that allow biFigure 1. 1cc computer [3] (left) and a 2.2×1.1×0.8 mm stacked miniature wireless sensor node [6] (right). directional wires, due to high active power. For instance, I2C [5] requires only 4 pads per module, but uses a kΩ-range pull-up resistor resulting in 100’s of μW of power draw, which is 100× the typical power budget of a millimeter-scale sensor node. Standby power management. In standby mode, power consumption must be reduced to the nW range to enable long lifetimes with millimeter batteries and perpetual operation with harvesting. This requires aggressive power gating and a PMU that can switch to an ultra-low, nW power mode. To avoid additional wires for communicating wakeup events, the bus interface must support a wakeup request originating from any node. This poses two challenges: 1) The logic that monitors/transmits such an event must be minimized since it remains always active and directly contributes to the standby power; 2) When the wakeup request is transmitted in the bus, the PMU is still in standby mode, meaning that active current draw used for this transmission cannot exceed the nA range. Fully synthesizable. Use of custom designed components significantly increases time and effort to migrate between technologies and impedes adoption. For example, the I2C variant in [6] used custom drivers, ratioed logic, and delay chains that require post-silicon tuning. A synthesizable bus interface not only allows fast design by “dropping-in” fully verified Verilog, it also ensures robust timing which is automatically checked by tools. However, disallowing more complex circuit structures increases the challenges to meet the low wire-count and power draw requirements. Systems Constraints. Finally, to be a viable system bus, MBus must provide multi-master operation, a robust reset mechanism, and dataand device-independent behavior. DESIGN & IMPLEMENTATION Each MBus node has four signals: DOUT, DIN, CLKOUT, and CLKIN. MBus nodes are arranged in ring topology, as shown in Fig. 2, connecting DOUT/CLKOUT to the next node’s DIN/CLKIN and eventually looping back. Signals “shootthrough”, and nodes have no local clock. One node must be a MBus mediator module. The mediator is responsible for generating the bus clock and mediating arbitration. While the bus is idle, regular nodes forward both DATA and CLK. The mediator breaks the loop by fixing both CLKOUT and DOUT high in idle/standby mode. To provide a robust, reliable inband, data-independent reset, MBus nodes feature a separate Interrupt Detector block that identifies an MBus Interrupt: At least three edges on DATA with no CLK edges. Fig. 3 shows the functional diagram of a single MBus node.
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CICC - MBus: A 17.5 pJ/bit/Chip portable interconnect bus for millimeter-scale sensor systems with 8 nW standby power
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014Co-Authors: Ye-sheng Kuo, Pat Pannuto, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, David Blaauw, Prabal Dutta, Inhee Lee, Yoonmyung LeeAbstract:We propose an ultra-low power interconnect bus for millimeter-scale wireless sensor nodes. Using only 4 IO pads, the bus minimizes the required Chip real estate, enabling ultrasmall form factors in modular sensor node designs. Low power is achieved using a “clockless” design of member nodes while aggressive power gating allows an ultra-low power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with PMUs that have a special low power standby mode. The MBus is fully synthesizable and uses robust timing. Implemented in a 3 module system in 180nm technology, Mbus achieves 8nW of standby power and 17.5 pJ/bit/Chip. Index Terms — Wireless sensor nodes, sensor systems, data buses, interconnections. INTRODUCTION Continued advances in ultra-low power circuit techniques have steadily moved the next generation of computer systems towards the vision of “smart dust” – a miniature, integrated sensing, computing, storage, and communication platform [1]. These systems are highly optimized in volume and power draw, targeting a mm3 form factor and running on single digit μW in active mode and nW in standby mode [2]. Early efforts [1][3] to realize such systems have resulted in monolithic and tightly integrated designs, with little capability for reuse. This design approach is in contrast to the modularity that has characterized embedded systems design and enabled it to address a highly diverse application space. The miniature sensor node application space is similarly diverse, ranging from implantable medical monitors to nearly invisible surveillance, to infrastructure monitoring. Hence, a modular design approach that enables extensive reuse of Chip modules is key to fully address its application space. A critical component in a modular platform is the bus through which the different modules communicate with each other. However, existing bus standards do not address the unique constraints of millimeter-scale sensor systems. We will show that the number of wires required in SPI [4] make it difficult to meet the millimeter size constraint while the power consumption of I2C [5] is orders of magnitude higher than the allowed power budget. Recently, a low power variant of I2C [6] was proposed for a modular millimeter sensor node, shown in Fig. 1, right. The system consists of several stacked Chip layers, each performing a key function (e.g, processor, memory, sensor interface, radio, etc.). However, the proposed bus requires careful matching of timing between nodes reducing robustness as well as requiring custom design, limiting portability. To address the unique constraints of millimeter-scale sensor nodes, we propose a new Chip-to-Chip bus interconnect, referred to as MBus, that is as conservative with resources as the modules it connects. MBus nodes are arranged in a ring topology, support multi-master communication, and use highly robust, fully synthesizable signaling. MBus uses only 4 IO pads, provides predictable latency, and features a novel, robust reset mechanism. To address the extreme low power constraints, member nodes in MBus are “clockless”. Also, all but 53 gates are power gated in standby mode while still enabling any node to wake up the entire system and switch the Power Management Unit (PMU) to active power mode. We present silicon measurements of a 3 layer sensor system implemented in 180 nm technology and achieve >10Mb/s data rate, with 17.55 pJ/bit/Chip and 8 nW standby power. SYSTEM INTERCONNECT DESIGN REQUIREMENTS In this section, we introduce the key design requirements for supporting ultra space-constrained systems and why this poses a unique challenge requiring a new bus interface. Low, fixed wire count per node. The target systems are highly space-constrained and even state-of-the-art wire bonding techniques require at least 35~65 μm/pad. When accounting for several power supply voltages and a few module-specific IOs, only a handful of pads remain for the bus interface in a 1 mm form factor. This makes the use of serial buses, such as SPI [4], difficult since they require a dedicated Chip-Select line for each component in the system. Hence, the maximum number of components needs to be anticipated ahead of time, often resulting in over-provisioning and a large total pad area. For instance, in a moderate 10 node system, the SPI controller would require at least 14 bus pads, which is impossible to realize in a millimeter-scale system. Low active power. A viable interface cannot dominate the μW power budget of millimeter sensors. This eliminates any pad-efficient open drain-based designs that allow biFigure 1. 1cc computer [3] (left) and a 2.2×1.1×0.8 mm stacked miniature wireless sensor node [6] (right). directional wires, due to high active power. For instance, I2C [5] requires only 4 pads per module, but uses a kΩ-range pull-up resistor resulting in 100’s of μW of power draw, which is 100× the typical power budget of a millimeter-scale sensor node. Standby power management. In standby mode, power consumption must be reduced to the nW range to enable long lifetimes with millimeter batteries and perpetual operation with harvesting. This requires aggressive power gating and a PMU that can switch to an ultra-low, nW power mode. To avoid additional wires for communicating wakeup events, the bus interface must support a wakeup request originating from any node. This poses two challenges: 1) The logic that monitors/transmits such an event must be minimized since it remains always active and directly contributes to the standby power; 2) When the wakeup request is transmitted in the bus, the PMU is still in standby mode, meaning that active current draw used for this transmission cannot exceed the nA range. Fully synthesizable. Use of custom designed components significantly increases time and effort to migrate between technologies and impedes adoption. For example, the I2C variant in [6] used custom drivers, ratioed logic, and delay chains that require post-silicon tuning. A synthesizable bus interface not only allows fast design by “dropping-in” fully verified Verilog, it also ensures robust timing which is automatically checked by tools. However, disallowing more complex circuit structures increases the challenges to meet the low wire-count and power draw requirements. Systems Constraints. Finally, to be a viable system bus, MBus must provide multi-master operation, a robust reset mechanism, and dataand device-independent behavior. DESIGN & IMPLEMENTATION Each MBus node has four signals: DOUT, DIN, CLKOUT, and CLKIN. MBus nodes are arranged in ring topology, as shown in Fig. 2, connecting DOUT/CLKOUT to the next node’s DIN/CLKIN and eventually looping back. Signals “shootthrough”, and nodes have no local clock. One node must be a MBus mediator module. The mediator is responsible for generating the bus clock and mediating arbitration. While the bus is idle, regular nodes forward both DATA and CLK. The mediator breaks the loop by fixing both CLKOUT and DOUT high in idle/standby mode. To provide a robust, reliable inband, data-independent reset, MBus nodes feature a separate Interrupt Detector block that identifies an MBus Interrupt: At least three edges on DATA with no CLK edges. Fig. 3 shows the functional diagram of a single MBus node.
Yoonmyung Lee - One of the best experts on this subject based on the ideXlab platform.
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MBus: A System Integration Bus for the Modular Microscale Computing Class
IEEE Micro, 2016Co-Authors: Pat Pannuto, Yoonmyung Lee, Ye-sheng Kuo, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, Prabal DuttaAbstract:I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized--yet reusable--components with an interconnect that permits tiny, ultra-low-power systems. In contrast to today's interconnects, which are limited by power-hungry pull-ups or high-overhead Chip Select lines, the authors' approach operates at lower power, with a fixed pin count, using fully synthesizable logic, and with surprisingly low-protocol overhead. The authors present MBus, a new four-pin, 22.6 pJ/bit/Chip Chip-to-Chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low-power system operation by automatically power gating each Chip in the system, easing the integration of active and inactive circuits. In addition, they introduce power-oblivious communication, which guarantees message reception even if the recipient is inactive. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that draw nanowatts.
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ISCA - MBus: an ultra-low power interconnect bus for next generation nanopower systems
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015Co-Authors: Pat Pannuto, Yoonmyung Lee, Ye-sheng Kuo, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, Prabal DuttaAbstract:As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized---yet reusable---components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead Chip-Select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/Chip Chip-to-Chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each Chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom Chips from three different semiconductor processes. A three-Chip, 2.2mm3 MBus system draws 8nW of total system standby power and uses only 22.6 pJ/bit/Chip for communication. This is the lowest power for any system bus with MBus's feature set.
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MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems.
Proceedings. International Symposium on Computer Architecture, 2015Co-Authors: Pat Pannuto, Yoonmyung Lee, Ye-sheng Kuo, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, Prabal DuttaAbstract:As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead Chip-Select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/Chip Chip-to-Chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each Chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom Chips from three different semiconductor processes. A three-Chip, 2.2 mm3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/Chip for communication. This is the lowest power for any system bus with MBus's feature set.
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mbus a 17 5 pj bit Chip portable interconnect bus for millimeter scale sensor systems with 8 nw standby power
Custom Integrated Circuits Conference, 2014Co-Authors: Ye-sheng Kuo, Pat Pannuto, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, David Blaauw, Prabal Dutta, Inhee Lee, Yoonmyung LeeAbstract:We propose an ultra-low power interconnect bus for millimeter-scale wireless sensor nodes. Using only 4 IO pads, the bus minimizes the required Chip real estate, enabling ultrasmall form factors in modular sensor node designs. Low power is achieved using a “clockless” design of member nodes while aggressive power gating allows an ultra-low power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with PMUs that have a special low power standby mode. The MBus is fully synthesizable and uses robust timing. Implemented in a 3 module system in 180nm technology, Mbus achieves 8nW of standby power and 17.5 pJ/bit/Chip. Index Terms — Wireless sensor nodes, sensor systems, data buses, interconnections. INTRODUCTION Continued advances in ultra-low power circuit techniques have steadily moved the next generation of computer systems towards the vision of “smart dust” – a miniature, integrated sensing, computing, storage, and communication platform [1]. These systems are highly optimized in volume and power draw, targeting a mm3 form factor and running on single digit μW in active mode and nW in standby mode [2]. Early efforts [1][3] to realize such systems have resulted in monolithic and tightly integrated designs, with little capability for reuse. This design approach is in contrast to the modularity that has characterized embedded systems design and enabled it to address a highly diverse application space. The miniature sensor node application space is similarly diverse, ranging from implantable medical monitors to nearly invisible surveillance, to infrastructure monitoring. Hence, a modular design approach that enables extensive reuse of Chip modules is key to fully address its application space. A critical component in a modular platform is the bus through which the different modules communicate with each other. However, existing bus standards do not address the unique constraints of millimeter-scale sensor systems. We will show that the number of wires required in SPI [4] make it difficult to meet the millimeter size constraint while the power consumption of I2C [5] is orders of magnitude higher than the allowed power budget. Recently, a low power variant of I2C [6] was proposed for a modular millimeter sensor node, shown in Fig. 1, right. The system consists of several stacked Chip layers, each performing a key function (e.g, processor, memory, sensor interface, radio, etc.). However, the proposed bus requires careful matching of timing between nodes reducing robustness as well as requiring custom design, limiting portability. To address the unique constraints of millimeter-scale sensor nodes, we propose a new Chip-to-Chip bus interconnect, referred to as MBus, that is as conservative with resources as the modules it connects. MBus nodes are arranged in a ring topology, support multi-master communication, and use highly robust, fully synthesizable signaling. MBus uses only 4 IO pads, provides predictable latency, and features a novel, robust reset mechanism. To address the extreme low power constraints, member nodes in MBus are “clockless”. Also, all but 53 gates are power gated in standby mode while still enabling any node to wake up the entire system and switch the Power Management Unit (PMU) to active power mode. We present silicon measurements of a 3 layer sensor system implemented in 180 nm technology and achieve >10Mb/s data rate, with 17.55 pJ/bit/Chip and 8 nW standby power. SYSTEM INTERCONNECT DESIGN REQUIREMENTS In this section, we introduce the key design requirements for supporting ultra space-constrained systems and why this poses a unique challenge requiring a new bus interface. Low, fixed wire count per node. The target systems are highly space-constrained and even state-of-the-art wire bonding techniques require at least 35~65 μm/pad. When accounting for several power supply voltages and a few module-specific IOs, only a handful of pads remain for the bus interface in a 1 mm form factor. This makes the use of serial buses, such as SPI [4], difficult since they require a dedicated Chip-Select line for each component in the system. Hence, the maximum number of components needs to be anticipated ahead of time, often resulting in over-provisioning and a large total pad area. For instance, in a moderate 10 node system, the SPI controller would require at least 14 bus pads, which is impossible to realize in a millimeter-scale system. Low active power. A viable interface cannot dominate the μW power budget of millimeter sensors. This eliminates any pad-efficient open drain-based designs that allow biFigure 1. 1cc computer [3] (left) and a 2.2×1.1×0.8 mm stacked miniature wireless sensor node [6] (right). directional wires, due to high active power. For instance, I2C [5] requires only 4 pads per module, but uses a kΩ-range pull-up resistor resulting in 100’s of μW of power draw, which is 100× the typical power budget of a millimeter-scale sensor node. Standby power management. In standby mode, power consumption must be reduced to the nW range to enable long lifetimes with millimeter batteries and perpetual operation with harvesting. This requires aggressive power gating and a PMU that can switch to an ultra-low, nW power mode. To avoid additional wires for communicating wakeup events, the bus interface must support a wakeup request originating from any node. This poses two challenges: 1) The logic that monitors/transmits such an event must be minimized since it remains always active and directly contributes to the standby power; 2) When the wakeup request is transmitted in the bus, the PMU is still in standby mode, meaning that active current draw used for this transmission cannot exceed the nA range. Fully synthesizable. Use of custom designed components significantly increases time and effort to migrate between technologies and impedes adoption. For example, the I2C variant in [6] used custom drivers, ratioed logic, and delay chains that require post-silicon tuning. A synthesizable bus interface not only allows fast design by “dropping-in” fully verified Verilog, it also ensures robust timing which is automatically checked by tools. However, disallowing more complex circuit structures increases the challenges to meet the low wire-count and power draw requirements. Systems Constraints. Finally, to be a viable system bus, MBus must provide multi-master operation, a robust reset mechanism, and dataand device-independent behavior. DESIGN & IMPLEMENTATION Each MBus node has four signals: DOUT, DIN, CLKOUT, and CLKIN. MBus nodes are arranged in ring topology, as shown in Fig. 2, connecting DOUT/CLKOUT to the next node’s DIN/CLKIN and eventually looping back. Signals “shootthrough”, and nodes have no local clock. One node must be a MBus mediator module. The mediator is responsible for generating the bus clock and mediating arbitration. While the bus is idle, regular nodes forward both DATA and CLK. The mediator breaks the loop by fixing both CLKOUT and DOUT high in idle/standby mode. To provide a robust, reliable inband, data-independent reset, MBus nodes feature a separate Interrupt Detector block that identifies an MBus Interrupt: At least three edges on DATA with no CLK edges. Fig. 3 shows the functional diagram of a single MBus node.
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CICC - MBus: A 17.5 pJ/bit/Chip portable interconnect bus for millimeter-scale sensor systems with 8 nW standby power
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014Co-Authors: Ye-sheng Kuo, Pat Pannuto, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, David Blaauw, Prabal Dutta, Inhee Lee, Yoonmyung LeeAbstract:We propose an ultra-low power interconnect bus for millimeter-scale wireless sensor nodes. Using only 4 IO pads, the bus minimizes the required Chip real estate, enabling ultrasmall form factors in modular sensor node designs. Low power is achieved using a “clockless” design of member nodes while aggressive power gating allows an ultra-low power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with PMUs that have a special low power standby mode. The MBus is fully synthesizable and uses robust timing. Implemented in a 3 module system in 180nm technology, Mbus achieves 8nW of standby power and 17.5 pJ/bit/Chip. Index Terms — Wireless sensor nodes, sensor systems, data buses, interconnections. INTRODUCTION Continued advances in ultra-low power circuit techniques have steadily moved the next generation of computer systems towards the vision of “smart dust” – a miniature, integrated sensing, computing, storage, and communication platform [1]. These systems are highly optimized in volume and power draw, targeting a mm3 form factor and running on single digit μW in active mode and nW in standby mode [2]. Early efforts [1][3] to realize such systems have resulted in monolithic and tightly integrated designs, with little capability for reuse. This design approach is in contrast to the modularity that has characterized embedded systems design and enabled it to address a highly diverse application space. The miniature sensor node application space is similarly diverse, ranging from implantable medical monitors to nearly invisible surveillance, to infrastructure monitoring. Hence, a modular design approach that enables extensive reuse of Chip modules is key to fully address its application space. A critical component in a modular platform is the bus through which the different modules communicate with each other. However, existing bus standards do not address the unique constraints of millimeter-scale sensor systems. We will show that the number of wires required in SPI [4] make it difficult to meet the millimeter size constraint while the power consumption of I2C [5] is orders of magnitude higher than the allowed power budget. Recently, a low power variant of I2C [6] was proposed for a modular millimeter sensor node, shown in Fig. 1, right. The system consists of several stacked Chip layers, each performing a key function (e.g, processor, memory, sensor interface, radio, etc.). However, the proposed bus requires careful matching of timing between nodes reducing robustness as well as requiring custom design, limiting portability. To address the unique constraints of millimeter-scale sensor nodes, we propose a new Chip-to-Chip bus interconnect, referred to as MBus, that is as conservative with resources as the modules it connects. MBus nodes are arranged in a ring topology, support multi-master communication, and use highly robust, fully synthesizable signaling. MBus uses only 4 IO pads, provides predictable latency, and features a novel, robust reset mechanism. To address the extreme low power constraints, member nodes in MBus are “clockless”. Also, all but 53 gates are power gated in standby mode while still enabling any node to wake up the entire system and switch the Power Management Unit (PMU) to active power mode. We present silicon measurements of a 3 layer sensor system implemented in 180 nm technology and achieve >10Mb/s data rate, with 17.55 pJ/bit/Chip and 8 nW standby power. SYSTEM INTERCONNECT DESIGN REQUIREMENTS In this section, we introduce the key design requirements for supporting ultra space-constrained systems and why this poses a unique challenge requiring a new bus interface. Low, fixed wire count per node. The target systems are highly space-constrained and even state-of-the-art wire bonding techniques require at least 35~65 μm/pad. When accounting for several power supply voltages and a few module-specific IOs, only a handful of pads remain for the bus interface in a 1 mm form factor. This makes the use of serial buses, such as SPI [4], difficult since they require a dedicated Chip-Select line for each component in the system. Hence, the maximum number of components needs to be anticipated ahead of time, often resulting in over-provisioning and a large total pad area. For instance, in a moderate 10 node system, the SPI controller would require at least 14 bus pads, which is impossible to realize in a millimeter-scale system. Low active power. A viable interface cannot dominate the μW power budget of millimeter sensors. This eliminates any pad-efficient open drain-based designs that allow biFigure 1. 1cc computer [3] (left) and a 2.2×1.1×0.8 mm stacked miniature wireless sensor node [6] (right). directional wires, due to high active power. For instance, I2C [5] requires only 4 pads per module, but uses a kΩ-range pull-up resistor resulting in 100’s of μW of power draw, which is 100× the typical power budget of a millimeter-scale sensor node. Standby power management. In standby mode, power consumption must be reduced to the nW range to enable long lifetimes with millimeter batteries and perpetual operation with harvesting. This requires aggressive power gating and a PMU that can switch to an ultra-low, nW power mode. To avoid additional wires for communicating wakeup events, the bus interface must support a wakeup request originating from any node. This poses two challenges: 1) The logic that monitors/transmits such an event must be minimized since it remains always active and directly contributes to the standby power; 2) When the wakeup request is transmitted in the bus, the PMU is still in standby mode, meaning that active current draw used for this transmission cannot exceed the nA range. Fully synthesizable. Use of custom designed components significantly increases time and effort to migrate between technologies and impedes adoption. For example, the I2C variant in [6] used custom drivers, ratioed logic, and delay chains that require post-silicon tuning. A synthesizable bus interface not only allows fast design by “dropping-in” fully verified Verilog, it also ensures robust timing which is automatically checked by tools. However, disallowing more complex circuit structures increases the challenges to meet the low wire-count and power draw requirements. Systems Constraints. Finally, to be a viable system bus, MBus must provide multi-master operation, a robust reset mechanism, and dataand device-independent behavior. DESIGN & IMPLEMENTATION Each MBus node has four signals: DOUT, DIN, CLKOUT, and CLKIN. MBus nodes are arranged in ring topology, as shown in Fig. 2, connecting DOUT/CLKOUT to the next node’s DIN/CLKIN and eventually looping back. Signals “shootthrough”, and nodes have no local clock. One node must be a MBus mediator module. The mediator is responsible for generating the bus clock and mediating arbitration. While the bus is idle, regular nodes forward both DATA and CLK. The mediator breaks the loop by fixing both CLKOUT and DOUT high in idle/standby mode. To provide a robust, reliable inband, data-independent reset, MBus nodes feature a separate Interrupt Detector block that identifies an MBus Interrupt: At least three edges on DATA with no CLK edges. Fig. 3 shows the functional diagram of a single MBus node.
Ye-sheng Kuo - One of the best experts on this subject based on the ideXlab platform.
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MBus: A System Integration Bus for the Modular Microscale Computing Class
IEEE Micro, 2016Co-Authors: Pat Pannuto, Yoonmyung Lee, Ye-sheng Kuo, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, Prabal DuttaAbstract:I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized--yet reusable--components with an interconnect that permits tiny, ultra-low-power systems. In contrast to today's interconnects, which are limited by power-hungry pull-ups or high-overhead Chip Select lines, the authors' approach operates at lower power, with a fixed pin count, using fully synthesizable logic, and with surprisingly low-protocol overhead. The authors present MBus, a new four-pin, 22.6 pJ/bit/Chip Chip-to-Chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low-power system operation by automatically power gating each Chip in the system, easing the integration of active and inactive circuits. In addition, they introduce power-oblivious communication, which guarantees message reception even if the recipient is inactive. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that draw nanowatts.
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ISCA - MBus: an ultra-low power interconnect bus for next generation nanopower systems
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015Co-Authors: Pat Pannuto, Yoonmyung Lee, Ye-sheng Kuo, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, Prabal DuttaAbstract:As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized---yet reusable---components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead Chip-Select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/Chip Chip-to-Chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each Chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom Chips from three different semiconductor processes. A three-Chip, 2.2mm3 MBus system draws 8nW of total system standby power and uses only 22.6 pJ/bit/Chip for communication. This is the lowest power for any system bus with MBus's feature set.
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MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems.
Proceedings. International Symposium on Computer Architecture, 2015Co-Authors: Pat Pannuto, Yoonmyung Lee, Ye-sheng Kuo, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, Prabal DuttaAbstract:As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead Chip-Select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/Chip Chip-to-Chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each Chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom Chips from three different semiconductor processes. A three-Chip, 2.2 mm3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/Chip for communication. This is the lowest power for any system bus with MBus's feature set.
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mbus a 17 5 pj bit Chip portable interconnect bus for millimeter scale sensor systems with 8 nw standby power
Custom Integrated Circuits Conference, 2014Co-Authors: Ye-sheng Kuo, Pat Pannuto, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, David Blaauw, Prabal Dutta, Inhee Lee, Yoonmyung LeeAbstract:We propose an ultra-low power interconnect bus for millimeter-scale wireless sensor nodes. Using only 4 IO pads, the bus minimizes the required Chip real estate, enabling ultrasmall form factors in modular sensor node designs. Low power is achieved using a “clockless” design of member nodes while aggressive power gating allows an ultra-low power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with PMUs that have a special low power standby mode. The MBus is fully synthesizable and uses robust timing. Implemented in a 3 module system in 180nm technology, Mbus achieves 8nW of standby power and 17.5 pJ/bit/Chip. Index Terms — Wireless sensor nodes, sensor systems, data buses, interconnections. INTRODUCTION Continued advances in ultra-low power circuit techniques have steadily moved the next generation of computer systems towards the vision of “smart dust” – a miniature, integrated sensing, computing, storage, and communication platform [1]. These systems are highly optimized in volume and power draw, targeting a mm3 form factor and running on single digit μW in active mode and nW in standby mode [2]. Early efforts [1][3] to realize such systems have resulted in monolithic and tightly integrated designs, with little capability for reuse. This design approach is in contrast to the modularity that has characterized embedded systems design and enabled it to address a highly diverse application space. The miniature sensor node application space is similarly diverse, ranging from implantable medical monitors to nearly invisible surveillance, to infrastructure monitoring. Hence, a modular design approach that enables extensive reuse of Chip modules is key to fully address its application space. A critical component in a modular platform is the bus through which the different modules communicate with each other. However, existing bus standards do not address the unique constraints of millimeter-scale sensor systems. We will show that the number of wires required in SPI [4] make it difficult to meet the millimeter size constraint while the power consumption of I2C [5] is orders of magnitude higher than the allowed power budget. Recently, a low power variant of I2C [6] was proposed for a modular millimeter sensor node, shown in Fig. 1, right. The system consists of several stacked Chip layers, each performing a key function (e.g, processor, memory, sensor interface, radio, etc.). However, the proposed bus requires careful matching of timing between nodes reducing robustness as well as requiring custom design, limiting portability. To address the unique constraints of millimeter-scale sensor nodes, we propose a new Chip-to-Chip bus interconnect, referred to as MBus, that is as conservative with resources as the modules it connects. MBus nodes are arranged in a ring topology, support multi-master communication, and use highly robust, fully synthesizable signaling. MBus uses only 4 IO pads, provides predictable latency, and features a novel, robust reset mechanism. To address the extreme low power constraints, member nodes in MBus are “clockless”. Also, all but 53 gates are power gated in standby mode while still enabling any node to wake up the entire system and switch the Power Management Unit (PMU) to active power mode. We present silicon measurements of a 3 layer sensor system implemented in 180 nm technology and achieve >10Mb/s data rate, with 17.55 pJ/bit/Chip and 8 nW standby power. SYSTEM INTERCONNECT DESIGN REQUIREMENTS In this section, we introduce the key design requirements for supporting ultra space-constrained systems and why this poses a unique challenge requiring a new bus interface. Low, fixed wire count per node. The target systems are highly space-constrained and even state-of-the-art wire bonding techniques require at least 35~65 μm/pad. When accounting for several power supply voltages and a few module-specific IOs, only a handful of pads remain for the bus interface in a 1 mm form factor. This makes the use of serial buses, such as SPI [4], difficult since they require a dedicated Chip-Select line for each component in the system. Hence, the maximum number of components needs to be anticipated ahead of time, often resulting in over-provisioning and a large total pad area. For instance, in a moderate 10 node system, the SPI controller would require at least 14 bus pads, which is impossible to realize in a millimeter-scale system. Low active power. A viable interface cannot dominate the μW power budget of millimeter sensors. This eliminates any pad-efficient open drain-based designs that allow biFigure 1. 1cc computer [3] (left) and a 2.2×1.1×0.8 mm stacked miniature wireless sensor node [6] (right). directional wires, due to high active power. For instance, I2C [5] requires only 4 pads per module, but uses a kΩ-range pull-up resistor resulting in 100’s of μW of power draw, which is 100× the typical power budget of a millimeter-scale sensor node. Standby power management. In standby mode, power consumption must be reduced to the nW range to enable long lifetimes with millimeter batteries and perpetual operation with harvesting. This requires aggressive power gating and a PMU that can switch to an ultra-low, nW power mode. To avoid additional wires for communicating wakeup events, the bus interface must support a wakeup request originating from any node. This poses two challenges: 1) The logic that monitors/transmits such an event must be minimized since it remains always active and directly contributes to the standby power; 2) When the wakeup request is transmitted in the bus, the PMU is still in standby mode, meaning that active current draw used for this transmission cannot exceed the nA range. Fully synthesizable. Use of custom designed components significantly increases time and effort to migrate between technologies and impedes adoption. For example, the I2C variant in [6] used custom drivers, ratioed logic, and delay chains that require post-silicon tuning. A synthesizable bus interface not only allows fast design by “dropping-in” fully verified Verilog, it also ensures robust timing which is automatically checked by tools. However, disallowing more complex circuit structures increases the challenges to meet the low wire-count and power draw requirements. Systems Constraints. Finally, to be a viable system bus, MBus must provide multi-master operation, a robust reset mechanism, and dataand device-independent behavior. DESIGN & IMPLEMENTATION Each MBus node has four signals: DOUT, DIN, CLKOUT, and CLKIN. MBus nodes are arranged in ring topology, as shown in Fig. 2, connecting DOUT/CLKOUT to the next node’s DIN/CLKIN and eventually looping back. Signals “shootthrough”, and nodes have no local clock. One node must be a MBus mediator module. The mediator is responsible for generating the bus clock and mediating arbitration. While the bus is idle, regular nodes forward both DATA and CLK. The mediator breaks the loop by fixing both CLKOUT and DOUT high in idle/standby mode. To provide a robust, reliable inband, data-independent reset, MBus nodes feature a separate Interrupt Detector block that identifies an MBus Interrupt: At least three edges on DATA with no CLK edges. Fig. 3 shows the functional diagram of a single MBus node.
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CICC - MBus: A 17.5 pJ/bit/Chip portable interconnect bus for millimeter-scale sensor systems with 8 nW standby power
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014Co-Authors: Ye-sheng Kuo, Pat Pannuto, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, David Blaauw, Prabal Dutta, Inhee Lee, Yoonmyung LeeAbstract:We propose an ultra-low power interconnect bus for millimeter-scale wireless sensor nodes. Using only 4 IO pads, the bus minimizes the required Chip real estate, enabling ultrasmall form factors in modular sensor node designs. Low power is achieved using a “clockless” design of member nodes while aggressive power gating allows an ultra-low power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with PMUs that have a special low power standby mode. The MBus is fully synthesizable and uses robust timing. Implemented in a 3 module system in 180nm technology, Mbus achieves 8nW of standby power and 17.5 pJ/bit/Chip. Index Terms — Wireless sensor nodes, sensor systems, data buses, interconnections. INTRODUCTION Continued advances in ultra-low power circuit techniques have steadily moved the next generation of computer systems towards the vision of “smart dust” – a miniature, integrated sensing, computing, storage, and communication platform [1]. These systems are highly optimized in volume and power draw, targeting a mm3 form factor and running on single digit μW in active mode and nW in standby mode [2]. Early efforts [1][3] to realize such systems have resulted in monolithic and tightly integrated designs, with little capability for reuse. This design approach is in contrast to the modularity that has characterized embedded systems design and enabled it to address a highly diverse application space. The miniature sensor node application space is similarly diverse, ranging from implantable medical monitors to nearly invisible surveillance, to infrastructure monitoring. Hence, a modular design approach that enables extensive reuse of Chip modules is key to fully address its application space. A critical component in a modular platform is the bus through which the different modules communicate with each other. However, existing bus standards do not address the unique constraints of millimeter-scale sensor systems. We will show that the number of wires required in SPI [4] make it difficult to meet the millimeter size constraint while the power consumption of I2C [5] is orders of magnitude higher than the allowed power budget. Recently, a low power variant of I2C [6] was proposed for a modular millimeter sensor node, shown in Fig. 1, right. The system consists of several stacked Chip layers, each performing a key function (e.g, processor, memory, sensor interface, radio, etc.). However, the proposed bus requires careful matching of timing between nodes reducing robustness as well as requiring custom design, limiting portability. To address the unique constraints of millimeter-scale sensor nodes, we propose a new Chip-to-Chip bus interconnect, referred to as MBus, that is as conservative with resources as the modules it connects. MBus nodes are arranged in a ring topology, support multi-master communication, and use highly robust, fully synthesizable signaling. MBus uses only 4 IO pads, provides predictable latency, and features a novel, robust reset mechanism. To address the extreme low power constraints, member nodes in MBus are “clockless”. Also, all but 53 gates are power gated in standby mode while still enabling any node to wake up the entire system and switch the Power Management Unit (PMU) to active power mode. We present silicon measurements of a 3 layer sensor system implemented in 180 nm technology and achieve >10Mb/s data rate, with 17.55 pJ/bit/Chip and 8 nW standby power. SYSTEM INTERCONNECT DESIGN REQUIREMENTS In this section, we introduce the key design requirements for supporting ultra space-constrained systems and why this poses a unique challenge requiring a new bus interface. Low, fixed wire count per node. The target systems are highly space-constrained and even state-of-the-art wire bonding techniques require at least 35~65 μm/pad. When accounting for several power supply voltages and a few module-specific IOs, only a handful of pads remain for the bus interface in a 1 mm form factor. This makes the use of serial buses, such as SPI [4], difficult since they require a dedicated Chip-Select line for each component in the system. Hence, the maximum number of components needs to be anticipated ahead of time, often resulting in over-provisioning and a large total pad area. For instance, in a moderate 10 node system, the SPI controller would require at least 14 bus pads, which is impossible to realize in a millimeter-scale system. Low active power. A viable interface cannot dominate the μW power budget of millimeter sensors. This eliminates any pad-efficient open drain-based designs that allow biFigure 1. 1cc computer [3] (left) and a 2.2×1.1×0.8 mm stacked miniature wireless sensor node [6] (right). directional wires, due to high active power. For instance, I2C [5] requires only 4 pads per module, but uses a kΩ-range pull-up resistor resulting in 100’s of μW of power draw, which is 100× the typical power budget of a millimeter-scale sensor node. Standby power management. In standby mode, power consumption must be reduced to the nW range to enable long lifetimes with millimeter batteries and perpetual operation with harvesting. This requires aggressive power gating and a PMU that can switch to an ultra-low, nW power mode. To avoid additional wires for communicating wakeup events, the bus interface must support a wakeup request originating from any node. This poses two challenges: 1) The logic that monitors/transmits such an event must be minimized since it remains always active and directly contributes to the standby power; 2) When the wakeup request is transmitted in the bus, the PMU is still in standby mode, meaning that active current draw used for this transmission cannot exceed the nA range. Fully synthesizable. Use of custom designed components significantly increases time and effort to migrate between technologies and impedes adoption. For example, the I2C variant in [6] used custom drivers, ratioed logic, and delay chains that require post-silicon tuning. A synthesizable bus interface not only allows fast design by “dropping-in” fully verified Verilog, it also ensures robust timing which is automatically checked by tools. However, disallowing more complex circuit structures increases the challenges to meet the low wire-count and power draw requirements. Systems Constraints. Finally, to be a viable system bus, MBus must provide multi-master operation, a robust reset mechanism, and dataand device-independent behavior. DESIGN & IMPLEMENTATION Each MBus node has four signals: DOUT, DIN, CLKOUT, and CLKIN. MBus nodes are arranged in ring topology, as shown in Fig. 2, connecting DOUT/CLKOUT to the next node’s DIN/CLKIN and eventually looping back. Signals “shootthrough”, and nodes have no local clock. One node must be a MBus mediator module. The mediator is responsible for generating the bus clock and mediating arbitration. While the bus is idle, regular nodes forward both DATA and CLK. The mediator breaks the loop by fixing both CLKOUT and DOUT high in idle/standby mode. To provide a robust, reliable inband, data-independent reset, MBus nodes feature a separate Interrupt Detector block that identifies an MBus Interrupt: At least three edges on DATA with no CLK edges. Fig. 3 shows the functional diagram of a single MBus node.
Gyouho Kim - One of the best experts on this subject based on the ideXlab platform.
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MBus: A System Integration Bus for the Modular Microscale Computing Class
IEEE Micro, 2016Co-Authors: Pat Pannuto, Yoonmyung Lee, Ye-sheng Kuo, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, Prabal DuttaAbstract:I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized--yet reusable--components with an interconnect that permits tiny, ultra-low-power systems. In contrast to today's interconnects, which are limited by power-hungry pull-ups or high-overhead Chip Select lines, the authors' approach operates at lower power, with a fixed pin count, using fully synthesizable logic, and with surprisingly low-protocol overhead. The authors present MBus, a new four-pin, 22.6 pJ/bit/Chip Chip-to-Chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low-power system operation by automatically power gating each Chip in the system, easing the integration of active and inactive circuits. In addition, they introduce power-oblivious communication, which guarantees message reception even if the recipient is inactive. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that draw nanowatts.
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ISCA - MBus: an ultra-low power interconnect bus for next generation nanopower systems
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015Co-Authors: Pat Pannuto, Yoonmyung Lee, Ye-sheng Kuo, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, Prabal DuttaAbstract:As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized---yet reusable---components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead Chip-Select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/Chip Chip-to-Chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each Chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom Chips from three different semiconductor processes. A three-Chip, 2.2mm3 MBus system draws 8nW of total system standby power and uses only 22.6 pJ/bit/Chip for communication. This is the lowest power for any system bus with MBus's feature set.
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MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems.
Proceedings. International Symposium on Computer Architecture, 2015Co-Authors: Pat Pannuto, Yoonmyung Lee, Ye-sheng Kuo, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, Prabal DuttaAbstract:As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead Chip-Select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/Chip Chip-to-Chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each Chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom Chips from three different semiconductor processes. A three-Chip, 2.2 mm3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/Chip for communication. This is the lowest power for any system bus with MBus's feature set.
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mbus a 17 5 pj bit Chip portable interconnect bus for millimeter scale sensor systems with 8 nw standby power
Custom Integrated Circuits Conference, 2014Co-Authors: Ye-sheng Kuo, Pat Pannuto, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, David Blaauw, Prabal Dutta, Inhee Lee, Yoonmyung LeeAbstract:We propose an ultra-low power interconnect bus for millimeter-scale wireless sensor nodes. Using only 4 IO pads, the bus minimizes the required Chip real estate, enabling ultrasmall form factors in modular sensor node designs. Low power is achieved using a “clockless” design of member nodes while aggressive power gating allows an ultra-low power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with PMUs that have a special low power standby mode. The MBus is fully synthesizable and uses robust timing. Implemented in a 3 module system in 180nm technology, Mbus achieves 8nW of standby power and 17.5 pJ/bit/Chip. Index Terms — Wireless sensor nodes, sensor systems, data buses, interconnections. INTRODUCTION Continued advances in ultra-low power circuit techniques have steadily moved the next generation of computer systems towards the vision of “smart dust” – a miniature, integrated sensing, computing, storage, and communication platform [1]. These systems are highly optimized in volume and power draw, targeting a mm3 form factor and running on single digit μW in active mode and nW in standby mode [2]. Early efforts [1][3] to realize such systems have resulted in monolithic and tightly integrated designs, with little capability for reuse. This design approach is in contrast to the modularity that has characterized embedded systems design and enabled it to address a highly diverse application space. The miniature sensor node application space is similarly diverse, ranging from implantable medical monitors to nearly invisible surveillance, to infrastructure monitoring. Hence, a modular design approach that enables extensive reuse of Chip modules is key to fully address its application space. A critical component in a modular platform is the bus through which the different modules communicate with each other. However, existing bus standards do not address the unique constraints of millimeter-scale sensor systems. We will show that the number of wires required in SPI [4] make it difficult to meet the millimeter size constraint while the power consumption of I2C [5] is orders of magnitude higher than the allowed power budget. Recently, a low power variant of I2C [6] was proposed for a modular millimeter sensor node, shown in Fig. 1, right. The system consists of several stacked Chip layers, each performing a key function (e.g, processor, memory, sensor interface, radio, etc.). However, the proposed bus requires careful matching of timing between nodes reducing robustness as well as requiring custom design, limiting portability. To address the unique constraints of millimeter-scale sensor nodes, we propose a new Chip-to-Chip bus interconnect, referred to as MBus, that is as conservative with resources as the modules it connects. MBus nodes are arranged in a ring topology, support multi-master communication, and use highly robust, fully synthesizable signaling. MBus uses only 4 IO pads, provides predictable latency, and features a novel, robust reset mechanism. To address the extreme low power constraints, member nodes in MBus are “clockless”. Also, all but 53 gates are power gated in standby mode while still enabling any node to wake up the entire system and switch the Power Management Unit (PMU) to active power mode. We present silicon measurements of a 3 layer sensor system implemented in 180 nm technology and achieve >10Mb/s data rate, with 17.55 pJ/bit/Chip and 8 nW standby power. SYSTEM INTERCONNECT DESIGN REQUIREMENTS In this section, we introduce the key design requirements for supporting ultra space-constrained systems and why this poses a unique challenge requiring a new bus interface. Low, fixed wire count per node. The target systems are highly space-constrained and even state-of-the-art wire bonding techniques require at least 35~65 μm/pad. When accounting for several power supply voltages and a few module-specific IOs, only a handful of pads remain for the bus interface in a 1 mm form factor. This makes the use of serial buses, such as SPI [4], difficult since they require a dedicated Chip-Select line for each component in the system. Hence, the maximum number of components needs to be anticipated ahead of time, often resulting in over-provisioning and a large total pad area. For instance, in a moderate 10 node system, the SPI controller would require at least 14 bus pads, which is impossible to realize in a millimeter-scale system. Low active power. A viable interface cannot dominate the μW power budget of millimeter sensors. This eliminates any pad-efficient open drain-based designs that allow biFigure 1. 1cc computer [3] (left) and a 2.2×1.1×0.8 mm stacked miniature wireless sensor node [6] (right). directional wires, due to high active power. For instance, I2C [5] requires only 4 pads per module, but uses a kΩ-range pull-up resistor resulting in 100’s of μW of power draw, which is 100× the typical power budget of a millimeter-scale sensor node. Standby power management. In standby mode, power consumption must be reduced to the nW range to enable long lifetimes with millimeter batteries and perpetual operation with harvesting. This requires aggressive power gating and a PMU that can switch to an ultra-low, nW power mode. To avoid additional wires for communicating wakeup events, the bus interface must support a wakeup request originating from any node. This poses two challenges: 1) The logic that monitors/transmits such an event must be minimized since it remains always active and directly contributes to the standby power; 2) When the wakeup request is transmitted in the bus, the PMU is still in standby mode, meaning that active current draw used for this transmission cannot exceed the nA range. Fully synthesizable. Use of custom designed components significantly increases time and effort to migrate between technologies and impedes adoption. For example, the I2C variant in [6] used custom drivers, ratioed logic, and delay chains that require post-silicon tuning. A synthesizable bus interface not only allows fast design by “dropping-in” fully verified Verilog, it also ensures robust timing which is automatically checked by tools. However, disallowing more complex circuit structures increases the challenges to meet the low wire-count and power draw requirements. Systems Constraints. Finally, to be a viable system bus, MBus must provide multi-master operation, a robust reset mechanism, and dataand device-independent behavior. DESIGN & IMPLEMENTATION Each MBus node has four signals: DOUT, DIN, CLKOUT, and CLKIN. MBus nodes are arranged in ring topology, as shown in Fig. 2, connecting DOUT/CLKOUT to the next node’s DIN/CLKIN and eventually looping back. Signals “shootthrough”, and nodes have no local clock. One node must be a MBus mediator module. The mediator is responsible for generating the bus clock and mediating arbitration. While the bus is idle, regular nodes forward both DATA and CLK. The mediator breaks the loop by fixing both CLKOUT and DOUT high in idle/standby mode. To provide a robust, reliable inband, data-independent reset, MBus nodes feature a separate Interrupt Detector block that identifies an MBus Interrupt: At least three edges on DATA with no CLK edges. Fig. 3 shows the functional diagram of a single MBus node.
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CICC - MBus: A 17.5 pJ/bit/Chip portable interconnect bus for millimeter-scale sensor systems with 8 nW standby power
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014Co-Authors: Ye-sheng Kuo, Pat Pannuto, Zhiyoong Foo, Benjamin Kempke, Gyouho Kim, David Blaauw, Prabal Dutta, Inhee Lee, Yoonmyung LeeAbstract:We propose an ultra-low power interconnect bus for millimeter-scale wireless sensor nodes. Using only 4 IO pads, the bus minimizes the required Chip real estate, enabling ultrasmall form factors in modular sensor node designs. Low power is achieved using a “clockless” design of member nodes while aggressive power gating allows an ultra-low power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with PMUs that have a special low power standby mode. The MBus is fully synthesizable and uses robust timing. Implemented in a 3 module system in 180nm technology, Mbus achieves 8nW of standby power and 17.5 pJ/bit/Chip. Index Terms — Wireless sensor nodes, sensor systems, data buses, interconnections. INTRODUCTION Continued advances in ultra-low power circuit techniques have steadily moved the next generation of computer systems towards the vision of “smart dust” – a miniature, integrated sensing, computing, storage, and communication platform [1]. These systems are highly optimized in volume and power draw, targeting a mm3 form factor and running on single digit μW in active mode and nW in standby mode [2]. Early efforts [1][3] to realize such systems have resulted in monolithic and tightly integrated designs, with little capability for reuse. This design approach is in contrast to the modularity that has characterized embedded systems design and enabled it to address a highly diverse application space. The miniature sensor node application space is similarly diverse, ranging from implantable medical monitors to nearly invisible surveillance, to infrastructure monitoring. Hence, a modular design approach that enables extensive reuse of Chip modules is key to fully address its application space. A critical component in a modular platform is the bus through which the different modules communicate with each other. However, existing bus standards do not address the unique constraints of millimeter-scale sensor systems. We will show that the number of wires required in SPI [4] make it difficult to meet the millimeter size constraint while the power consumption of I2C [5] is orders of magnitude higher than the allowed power budget. Recently, a low power variant of I2C [6] was proposed for a modular millimeter sensor node, shown in Fig. 1, right. The system consists of several stacked Chip layers, each performing a key function (e.g, processor, memory, sensor interface, radio, etc.). However, the proposed bus requires careful matching of timing between nodes reducing robustness as well as requiring custom design, limiting portability. To address the unique constraints of millimeter-scale sensor nodes, we propose a new Chip-to-Chip bus interconnect, referred to as MBus, that is as conservative with resources as the modules it connects. MBus nodes are arranged in a ring topology, support multi-master communication, and use highly robust, fully synthesizable signaling. MBus uses only 4 IO pads, provides predictable latency, and features a novel, robust reset mechanism. To address the extreme low power constraints, member nodes in MBus are “clockless”. Also, all but 53 gates are power gated in standby mode while still enabling any node to wake up the entire system and switch the Power Management Unit (PMU) to active power mode. We present silicon measurements of a 3 layer sensor system implemented in 180 nm technology and achieve >10Mb/s data rate, with 17.55 pJ/bit/Chip and 8 nW standby power. SYSTEM INTERCONNECT DESIGN REQUIREMENTS In this section, we introduce the key design requirements for supporting ultra space-constrained systems and why this poses a unique challenge requiring a new bus interface. Low, fixed wire count per node. The target systems are highly space-constrained and even state-of-the-art wire bonding techniques require at least 35~65 μm/pad. When accounting for several power supply voltages and a few module-specific IOs, only a handful of pads remain for the bus interface in a 1 mm form factor. This makes the use of serial buses, such as SPI [4], difficult since they require a dedicated Chip-Select line for each component in the system. Hence, the maximum number of components needs to be anticipated ahead of time, often resulting in over-provisioning and a large total pad area. For instance, in a moderate 10 node system, the SPI controller would require at least 14 bus pads, which is impossible to realize in a millimeter-scale system. Low active power. A viable interface cannot dominate the μW power budget of millimeter sensors. This eliminates any pad-efficient open drain-based designs that allow biFigure 1. 1cc computer [3] (left) and a 2.2×1.1×0.8 mm stacked miniature wireless sensor node [6] (right). directional wires, due to high active power. For instance, I2C [5] requires only 4 pads per module, but uses a kΩ-range pull-up resistor resulting in 100’s of μW of power draw, which is 100× the typical power budget of a millimeter-scale sensor node. Standby power management. In standby mode, power consumption must be reduced to the nW range to enable long lifetimes with millimeter batteries and perpetual operation with harvesting. This requires aggressive power gating and a PMU that can switch to an ultra-low, nW power mode. To avoid additional wires for communicating wakeup events, the bus interface must support a wakeup request originating from any node. This poses two challenges: 1) The logic that monitors/transmits such an event must be minimized since it remains always active and directly contributes to the standby power; 2) When the wakeup request is transmitted in the bus, the PMU is still in standby mode, meaning that active current draw used for this transmission cannot exceed the nA range. Fully synthesizable. Use of custom designed components significantly increases time and effort to migrate between technologies and impedes adoption. For example, the I2C variant in [6] used custom drivers, ratioed logic, and delay chains that require post-silicon tuning. A synthesizable bus interface not only allows fast design by “dropping-in” fully verified Verilog, it also ensures robust timing which is automatically checked by tools. However, disallowing more complex circuit structures increases the challenges to meet the low wire-count and power draw requirements. Systems Constraints. Finally, to be a viable system bus, MBus must provide multi-master operation, a robust reset mechanism, and dataand device-independent behavior. DESIGN & IMPLEMENTATION Each MBus node has four signals: DOUT, DIN, CLKOUT, and CLKIN. MBus nodes are arranged in ring topology, as shown in Fig. 2, connecting DOUT/CLKOUT to the next node’s DIN/CLKIN and eventually looping back. Signals “shootthrough”, and nodes have no local clock. One node must be a MBus mediator module. The mediator is responsible for generating the bus clock and mediating arbitration. While the bus is idle, regular nodes forward both DATA and CLK. The mediator breaks the loop by fixing both CLKOUT and DOUT high in idle/standby mode. To provide a robust, reliable inband, data-independent reset, MBus nodes feature a separate Interrupt Detector block that identifies an MBus Interrupt: At least three edges on DATA with no CLK edges. Fig. 3 shows the functional diagram of a single MBus node.