The Experts below are selected from a list of 30 Experts worldwide ranked by ideXlab platform
Li Zexia - One of the best experts on this subject based on the ideXlab platform.
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Tutorial on direct digital synthesizer structure improvements and static timing analysis
2021Co-Authors: Li ZexiaAbstract:The direct digital frequency synthesizer (DDS) has been widely used in digital communication systems due to its high frequency resolution, fast frequency conversion, and continuous phase change. With the development of microelectronics technology, field-programmable gate array (FPGA) devices have been rapidly developed. Because of FPGAs’ high Speed, high integration and field-programmable advantages, the devices are widely used in digital processing and are increasingly favored by hardware circuit design engineers. FPGAs also provide a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced to a fixed-frequency precision clock source. Many telecommunication applications require such high-Speed switching, fine tunability and superior quality signal source for their components. This thesis will introduce the direct digital synthesizer (DDS) and investigate some ways to optimize the DDS structure to save hardware resources and increase Chip Speed without sacrificing signal quality. The Verilog hardware description language is used as the development language. This thesis will describe entire designs of both DDS with traditional structure and DDS with new structures. By comparing the outputs, it also examines the corresponding simulation results and verifies the improvement of the signal quality.U of I OnlyAuthor requested U of Illinois access only (OA after 2yrs) in Vireo ETD syste
Li Zexian - One of the best experts on this subject based on the ideXlab platform.
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Tutorial on direct digital synthesizer structure improvements and static timing analysis
2018Co-Authors: Li ZexianAbstract:The direct digital frequency synthesizer (DDS) has been widely used in digital communication systems due to its high frequency resolution, fast frequency conversion, and continuous phase change. With the development of microelectronics technology, field-programmable gate array (FPGA) devices have been rapidly developed. Because of FPGAs’ high Speed, high integration and field-programmable advantages, the devices are widely used in digital processing and are increasingly favored by hardware circuit design engineers. FPGAs also provide a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced to a fixed-frequency precision clock source. Many telecommunication applications require such high-Speed switching, fine tunability and superior quality signal source for their components. This thesis will introduce the direct digital synthesizer (DDS) and investigate some ways to optimize the DDS structure to save hardware resources and increase Chip Speed without sacrificing signal quality. The Verilog hardware description language is used as the development language. This thesis will describe entire designs of both DDS with traditional structure and DDS with new structures. By comparing the outputs, it also examines the corresponding simulation results and verifies the improvement of the signal quality
Kaushik Roy - One of the best experts on this subject based on the ideXlab platform.
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a novel on Chip delay measurement hardware for efficient Speed binning
International On-Line Testing Symposium, 2005Co-Authors: Arijit Raychowdhury, Swaroop Ghosh, Kaushik RoyAbstract:With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spectrum. Consequently, Speed binning of the high performance VLSI Chips is essential and it costs significant amount of test application time. Further, the knowledge of the actual delay in the critical path of the circuit enables efficient use of typical low power methodologies e.g., voltage scaling, adaptive body biasing etc. In this paper, the authors have proposed a novel on-Chip, low overhead and process tolerant delay measurement circuit which can estimate the critical path delay in a single clock period. This has the advantage of efficient on-Chip Speed binning.
Arijit Raychowdhury - One of the best experts on this subject based on the ideXlab platform.
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a novel on Chip delay measurement hardware for efficient Speed binning
International On-Line Testing Symposium, 2005Co-Authors: Arijit Raychowdhury, Swaroop Ghosh, Kaushik RoyAbstract:With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spectrum. Consequently, Speed binning of the high performance VLSI Chips is essential and it costs significant amount of test application time. Further, the knowledge of the actual delay in the critical path of the circuit enables efficient use of typical low power methodologies e.g., voltage scaling, adaptive body biasing etc. In this paper, the authors have proposed a novel on-Chip, low overhead and process tolerant delay measurement circuit which can estimate the critical path delay in a single clock period. This has the advantage of efficient on-Chip Speed binning.
Swaroop Ghosh - One of the best experts on this subject based on the ideXlab platform.
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a novel on Chip delay measurement hardware for efficient Speed binning
International On-Line Testing Symposium, 2005Co-Authors: Arijit Raychowdhury, Swaroop Ghosh, Kaushik RoyAbstract:With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spectrum. Consequently, Speed binning of the high performance VLSI Chips is essential and it costs significant amount of test application time. Further, the knowledge of the actual delay in the critical path of the circuit enables efficient use of typical low power methodologies e.g., voltage scaling, adaptive body biasing etc. In this paper, the authors have proposed a novel on-Chip, low overhead and process tolerant delay measurement circuit which can estimate the critical path delay in a single clock period. This has the advantage of efficient on-Chip Speed binning.