The Experts below are selected from a list of 111 Experts worldwide ranked by ideXlab platform
Muhammad A. Alam - One of the best experts on this subject based on the ideXlab platform.
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Design Principles of Self-Compensated NBTI-Free Negative Capacitor FinFET
IEEE Transactions on Electron Devices, 2020Co-Authors: Karda Kamal M, Chandra Mouli, Muhammad A. AlamAbstract:The Landau field-effect transistors have been previously investiGated to lower the power dissipation of integrated circuits by reducing the subthreshold swing (SS) below the Boltzmann limit of 60 mV/dec. The basic idea is to replace the Classical Gate insulator with dielectrics that exhibit a negative capacitance (NC) associated with the double-well energy landscape, for example, ferroelectrics (FE), air-gap capacitors, or a combination thereof. In this article, we demonstrate that the same NC effect can also be used to achieve the devices more robust to negative-bias temperature instability (NBTI), which continues to be a major reliability challenge for scaled p-type transistors. We demonstrate that with careful design of an NC-based Landau switch, the intrinsic NBTI degradation can be fully compensated while still maintaining hysteresis-free operation and steeper slope needed for the logic switch. In fact, the parasitic capacitances in a FinFET counterintuitively make a negative capacitance field effect transistor (NCFET) more NBTI tolerant. The proposed device is validated using the numerical simulations by technologically relevant p-type SiGe FinFeTs. The results suggest the intriguing possibility that a careful, physics-informed NCFET design can simultaneously achieve reliability performance metrics.
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an anti ferroelectric Gated landau transistor to achieve sub 60 mv dec switching at low voltage and high speed
Applied Physics Letters, 2015Co-Authors: Ankit Jain, Kamal M Karda, Chandra Mouli, Muhammad A. AlamAbstract:Landau field effect transistors promise to lower the power-dissipation of integrated circuits (ICs) by reducing the subthreshold swing (S) below the Boltzmann limit of 60 mV/dec. The key idea is to replace the Classical Gate insulator with dielectrics that exhibit negative capacitance (NC) associated with double-well energy landscape, for example, ferroelectrics (FE), air-gap capacitors, or a combination thereof. Indeed, S is dramatically reduced, constrained only by the limits of hysteresis-free operation. Unfortunately, the following limitations apply (i) the need for capacitance matching constrains steep S only to the small subthreshold region for FE based negative capacitance field effect transistor (NCFET) and requires an insulator too thick for sub-20 nm scaling; (ii) the kinetics of mechanical switching for airgap based NCFET obviate high-speed operation; and (iii) the lattice mismatch between the substrate and the dielectric makes defect-free integration difficult. In this article, we demonstrate ...
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an anti ferroelectric Gated landau transistor to achieve sub 60 mv dec switching at low voltage and high speed
Applied Physics Letters, 2015Co-Authors: Ankit Jain, Kamal M Karda, Chandra Mouli, Muhammad A. AlamAbstract:Landau field effect transistors promise to lower the power-dissipation of integrated circuits (ICs) by reducing the subthreshold swing (S) below the Boltzmann limit of 60 mV/dec. The key idea is to replace the Classical Gate insulator with dielectrics that exhibit negative capacitance (NC) associated with double-well energy landscape, for example, ferroelectrics (FE), air-gap capacitors, or a combination thereof. Indeed, S is dramatically reduced, constrained only by the limits of hysteresis-free operation. Unfortunately, the following limitations apply (i) the need for capacitance matching constrains steep S only to the small subthreshold region for FE based negative capacitance field effect transistor (NCFET) and requires an insulator too thick for sub-20 nm scaling; (ii) the kinetics of mechanical switching for airgap based NCFET obviate high-speed operation; and (iii) the lattice mismatch between the substrate and the dielectric makes defect-free integration difficult. In this article, we demonstrate ...
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Hot atom damage (HAD) limited TDDB lifetime of ferroelectric memories
2013 IEEE International Electron Devices Meeting, 2013Co-Authors: Muhammad Masuduzzaman, Muhammad A. AlamAbstract:The AC/DC dielectric lifetime (TDDB) of ferroelectric materials have traditionally been interpreted similar to a Classical Gate oxide. In this paper, we demonstrate a fundamentally different kinetic mechanism of damage involving hot atom (HAD) in ferroelectric materials to interpret the severe reduction of AC lifetime, coupled with the counterintuitive increase in the Weibull slope. We show that, beyond a critical operating condition, the atoms at the domain walls are heated by the AC field, as they shuttle across the double-well energy landscape of such materials. An elegantly simple analytical model (i) interprets critical TDDB experiments, (ii) suggests strategies (e.g., pulse shaping) to minimize HAD significantly, and (iii) predicts device lifetime at arbitrary operating conditions.
Kamal M Karda - One of the best experts on this subject based on the ideXlab platform.
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an anti ferroelectric Gated landau transistor to achieve sub 60 mv dec switching at low voltage and high speed
Applied Physics Letters, 2015Co-Authors: Ankit Jain, Kamal M Karda, Chandra Mouli, Muhammad A. AlamAbstract:Landau field effect transistors promise to lower the power-dissipation of integrated circuits (ICs) by reducing the subthreshold swing (S) below the Boltzmann limit of 60 mV/dec. The key idea is to replace the Classical Gate insulator with dielectrics that exhibit negative capacitance (NC) associated with double-well energy landscape, for example, ferroelectrics (FE), air-gap capacitors, or a combination thereof. Indeed, S is dramatically reduced, constrained only by the limits of hysteresis-free operation. Unfortunately, the following limitations apply (i) the need for capacitance matching constrains steep S only to the small subthreshold region for FE based negative capacitance field effect transistor (NCFET) and requires an insulator too thick for sub-20 nm scaling; (ii) the kinetics of mechanical switching for airgap based NCFET obviate high-speed operation; and (iii) the lattice mismatch between the substrate and the dielectric makes defect-free integration difficult. In this article, we demonstrate ...
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an anti ferroelectric Gated landau transistor to achieve sub 60 mv dec switching at low voltage and high speed
Applied Physics Letters, 2015Co-Authors: Ankit Jain, Kamal M Karda, Chandra Mouli, Muhammad A. AlamAbstract:Landau field effect transistors promise to lower the power-dissipation of integrated circuits (ICs) by reducing the subthreshold swing (S) below the Boltzmann limit of 60 mV/dec. The key idea is to replace the Classical Gate insulator with dielectrics that exhibit negative capacitance (NC) associated with double-well energy landscape, for example, ferroelectrics (FE), air-gap capacitors, or a combination thereof. Indeed, S is dramatically reduced, constrained only by the limits of hysteresis-free operation. Unfortunately, the following limitations apply (i) the need for capacitance matching constrains steep S only to the small subthreshold region for FE based negative capacitance field effect transistor (NCFET) and requires an insulator too thick for sub-20 nm scaling; (ii) the kinetics of mechanical switching for airgap based NCFET obviate high-speed operation; and (iii) the lattice mismatch between the substrate and the dielectric makes defect-free integration difficult. In this article, we demonstrate ...
Chandra Mouli - One of the best experts on this subject based on the ideXlab platform.
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Design Principles of Self-Compensated NBTI-Free Negative Capacitor FinFET
IEEE Transactions on Electron Devices, 2020Co-Authors: Karda Kamal M, Chandra Mouli, Muhammad A. AlamAbstract:The Landau field-effect transistors have been previously investiGated to lower the power dissipation of integrated circuits by reducing the subthreshold swing (SS) below the Boltzmann limit of 60 mV/dec. The basic idea is to replace the Classical Gate insulator with dielectrics that exhibit a negative capacitance (NC) associated with the double-well energy landscape, for example, ferroelectrics (FE), air-gap capacitors, or a combination thereof. In this article, we demonstrate that the same NC effect can also be used to achieve the devices more robust to negative-bias temperature instability (NBTI), which continues to be a major reliability challenge for scaled p-type transistors. We demonstrate that with careful design of an NC-based Landau switch, the intrinsic NBTI degradation can be fully compensated while still maintaining hysteresis-free operation and steeper slope needed for the logic switch. In fact, the parasitic capacitances in a FinFET counterintuitively make a negative capacitance field effect transistor (NCFET) more NBTI tolerant. The proposed device is validated using the numerical simulations by technologically relevant p-type SiGe FinFeTs. The results suggest the intriguing possibility that a careful, physics-informed NCFET design can simultaneously achieve reliability performance metrics.
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an anti ferroelectric Gated landau transistor to achieve sub 60 mv dec switching at low voltage and high speed
Applied Physics Letters, 2015Co-Authors: Ankit Jain, Kamal M Karda, Chandra Mouli, Muhammad A. AlamAbstract:Landau field effect transistors promise to lower the power-dissipation of integrated circuits (ICs) by reducing the subthreshold swing (S) below the Boltzmann limit of 60 mV/dec. The key idea is to replace the Classical Gate insulator with dielectrics that exhibit negative capacitance (NC) associated with double-well energy landscape, for example, ferroelectrics (FE), air-gap capacitors, or a combination thereof. Indeed, S is dramatically reduced, constrained only by the limits of hysteresis-free operation. Unfortunately, the following limitations apply (i) the need for capacitance matching constrains steep S only to the small subthreshold region for FE based negative capacitance field effect transistor (NCFET) and requires an insulator too thick for sub-20 nm scaling; (ii) the kinetics of mechanical switching for airgap based NCFET obviate high-speed operation; and (iii) the lattice mismatch between the substrate and the dielectric makes defect-free integration difficult. In this article, we demonstrate ...
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an anti ferroelectric Gated landau transistor to achieve sub 60 mv dec switching at low voltage and high speed
Applied Physics Letters, 2015Co-Authors: Ankit Jain, Kamal M Karda, Chandra Mouli, Muhammad A. AlamAbstract:Landau field effect transistors promise to lower the power-dissipation of integrated circuits (ICs) by reducing the subthreshold swing (S) below the Boltzmann limit of 60 mV/dec. The key idea is to replace the Classical Gate insulator with dielectrics that exhibit negative capacitance (NC) associated with double-well energy landscape, for example, ferroelectrics (FE), air-gap capacitors, or a combination thereof. Indeed, S is dramatically reduced, constrained only by the limits of hysteresis-free operation. Unfortunately, the following limitations apply (i) the need for capacitance matching constrains steep S only to the small subthreshold region for FE based negative capacitance field effect transistor (NCFET) and requires an insulator too thick for sub-20 nm scaling; (ii) the kinetics of mechanical switching for airgap based NCFET obviate high-speed operation; and (iii) the lattice mismatch between the substrate and the dielectric makes defect-free integration difficult. In this article, we demonstrate ...
Ankit Jain - One of the best experts on this subject based on the ideXlab platform.
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an anti ferroelectric Gated landau transistor to achieve sub 60 mv dec switching at low voltage and high speed
Applied Physics Letters, 2015Co-Authors: Ankit Jain, Kamal M Karda, Chandra Mouli, Muhammad A. AlamAbstract:Landau field effect transistors promise to lower the power-dissipation of integrated circuits (ICs) by reducing the subthreshold swing (S) below the Boltzmann limit of 60 mV/dec. The key idea is to replace the Classical Gate insulator with dielectrics that exhibit negative capacitance (NC) associated with double-well energy landscape, for example, ferroelectrics (FE), air-gap capacitors, or a combination thereof. Indeed, S is dramatically reduced, constrained only by the limits of hysteresis-free operation. Unfortunately, the following limitations apply (i) the need for capacitance matching constrains steep S only to the small subthreshold region for FE based negative capacitance field effect transistor (NCFET) and requires an insulator too thick for sub-20 nm scaling; (ii) the kinetics of mechanical switching for airgap based NCFET obviate high-speed operation; and (iii) the lattice mismatch between the substrate and the dielectric makes defect-free integration difficult. In this article, we demonstrate ...
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an anti ferroelectric Gated landau transistor to achieve sub 60 mv dec switching at low voltage and high speed
Applied Physics Letters, 2015Co-Authors: Ankit Jain, Kamal M Karda, Chandra Mouli, Muhammad A. AlamAbstract:Landau field effect transistors promise to lower the power-dissipation of integrated circuits (ICs) by reducing the subthreshold swing (S) below the Boltzmann limit of 60 mV/dec. The key idea is to replace the Classical Gate insulator with dielectrics that exhibit negative capacitance (NC) associated with double-well energy landscape, for example, ferroelectrics (FE), air-gap capacitors, or a combination thereof. Indeed, S is dramatically reduced, constrained only by the limits of hysteresis-free operation. Unfortunately, the following limitations apply (i) the need for capacitance matching constrains steep S only to the small subthreshold region for FE based negative capacitance field effect transistor (NCFET) and requires an insulator too thick for sub-20 nm scaling; (ii) the kinetics of mechanical switching for airgap based NCFET obviate high-speed operation; and (iii) the lattice mismatch between the substrate and the dielectric makes defect-free integration difficult. In this article, we demonstrate ...
E. Kapetanakis - One of the best experts on this subject based on the ideXlab platform.
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Si and Ge nanocrystals for future memory devices
Materials Science in Semiconductor Processing, 2012Co-Authors: Caroline Bonafos, Marzia Carrada, Gérard Benassayag, Sylvie Schamm-chardon, Jesse Groenen, Vincent Paillard, Béatrice Pécassou, Alain Claverie, P. Dimitrakis, E. KapetanakisAbstract:An attractive alternative for extending the scaling of Flash-type memories is to replace the conventional floating Gate (a poly-Si layer) by laterally isolated floating nodes in the form of nanoparticles. This floating-Gate concept has led to the emergence of the so-called nanocrystal (NC) memories which have the potential of operating at lower voltages and higher speeds compared to the conventional non-volatile memories (NVMs) without compromising the criterion of non-volatility. NC memories also offer other advantages like a better immunity to the crosstalk effect arising from the floating-Gate coupling of closely spaced adjacent cells and an increased design flexibility from which quantum confinement phenomena can be judiciously exploited for enhanced memory functionality. Among the different technological routes explored in the last few years for generating nanocrystals in the Gate insulator of MOS devices, two major techniques have been utilized, namely deposition in vacuum and ion beam synthesis. During the last decade, we have extensively explored the ultra-low-energy ion-beam-synthesis (ULE-IBS) technique to produce single planes of Si-NCs in very thin (5–10 nm) insulator layers. This review summarizes more than 10 years of research efforts we and other groups have dedicated to the fabrication of NCs memories using this original technique. By exploiting the flexibility of the ULE-IBS route, Si-NCs single-transistor NVM cells using “Classical” Gate oxides (SiO2) have been successfully realized. More recently, advanced dielectric stacks employing high-κ dielectric (HfO2) as tunnel oxide and SiN as control oxide and host matrix for Si and Ge-NCs, have been fabricated and show promising performance for low-voltage operating-NVM devices. Particular emphasis is placed herein on material science issues such as anomalous and controlled oxidation processes. While much research is still needed for making reliable and competitive NC NVMs, our systematic investigations based on the ULE-IBS option demonstrate that a tight control and understanding of the properties of NCs memory cells can be achieved, provided that deep structural characterization is coupled to electrical studies.