The Experts below are selected from a list of 7431 Experts worldwide ranked by ideXlab platform
M. Figueiredo - One of the best experts on this subject based on the ideXlab platform.
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Resource constrained Clock Recovery on programmable logic devices
9th International Conference on Electronics Circuits and Systems, 1Co-Authors: R.l. Aguiar, M. FigueiredoAbstract:Clock Recovery is an important task in communications. With the usage of programmable logic devices as core elements in communication systems, the integration of Clock Recovery in programmable logic devices (PLDs) is highly desirable. This paper discusses some facilities being provided in recent families of PLDs for timing management, and shows new architectures oriented for the implementation of Clock Recovery circuits for high-speed communications using these facilities, in such a resource constrained environment. In particular, a 155 Mbps Clock Recovery unit using low cost Xilinx devices is discussed, and its performance is compared with more traditional methods.
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ICECS - Resource constrained Clock Recovery on programmable logic devices
9th International Conference on Electronics Circuits and Systems, 1Co-Authors: R.l. Aguiar, M. FigueiredoAbstract:Clock Recovery is an important task in communications. With the usage of programmable logic devices as core elements in communication systems, the integration of Clock Recovery in programmable logic devices (PLDs) is highly desirable. This paper discusses some facilities being provided in recent families of PLDs for timing management, and shows new architectures oriented for the implementation of Clock Recovery circuits for high-speed communications using these facilities, in such a resource constrained environment. In particular, a 155 Mbps Clock Recovery unit using low cost Xilinx devices is discussed, and its performance is compared with more traditional methods.
Shen Hai-bin - One of the best experts on this subject based on the ideXlab platform.
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Design of All-digital Clock Recovery Unit Based on USB Device
Computer Engineering, 2012Co-Authors: Shen Hai-binAbstract:This paper designs a kind of all-digital Clock Recovery unit based on USB full speed device to solve the problem that common Clock Recovery methods in USB full speed device are low accuracy or high cost.This Clock Recovery unit contains a module which can extract timing messages from USB bus data,and uses the digitally-controlled oscillator which can overcome the bad effect by the chip's different operating conditions.The design uses the all-digital circuit design processes,logic synthesis and PR process of which is based on the standard cell library.The result of this design satisfies the USB specification's requirements.
B.g. Bosch - One of the best experts on this subject based on the ideXlab platform.
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Multi-Gb/s silicon bipolar Clock Recovery IC
IEEE Journal on Selected Areas in Communications, 1991Co-Authors: Zhaoxin Wang, U. Langmann, B.g. BoschAbstract:A novel Clock Recovery IC for optical fiber communication systems with data rates up to several Gb/s is presented. It combines nonlinear signal preprocessing directly with a regenerative frequency divider scheme and an external filter in the divider loop. Hence, the center frequency of the filter and the working frequency of the amplifier are halved. The extracted Clock frequency corresponds to half the bit rate, as required for many Clocked circuit components within fiber optic lines. Two versions of the same IC design, scheduled for two bit rate ranges between 0.3-4 Gb/s, are realized with a conventional Si bipolar process. Clock Recovery is demonstrated at 2.2 and 3.52 Gb/s, using both cavity and surface acoustic wave (SAW) filters. >
Jian Shui-sheng - One of the best experts on this subject based on the ideXlab platform.
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A Simple Loop for Simultaneous OTDM Demultiplexing and Clock Recovery
Chinese Physics Letters, 2009Co-Authors: Chen He-ming, Lu Dan, Gong Tao-rong, Wang Mu-guang, Li Tangjun, Jian Shui-shengAbstract:A simple and stable loop consisting of a pair of concatenated electroabsorption modulators (EAMs) and 10 GHz Clock Recovery module is presented and demonstrated experimentally for simultaneous demultiplexing and Clock Recovery for OTDM networks. The 10Gb/s demultiplexed signal and 10 GHz recovered Clock are successfully implemented from 80 Gbit/s and 160 Gbit/s OTDM signals utilizing the loop. The loop based on EAM-PLL can provide excellent tolerance range (> 5 dB) of the OSCR of the source laser, and the recovered Clock signal exhibits low rms jitter over a dynamic input optical power range of 15 dB.
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Multiwavelength All-Optical Clock Recovery of Non-Return-to-Zero Data
Chinese Physics Letters, 2007Co-Authors: Zhang Feng, Chen He-ming, Lu Dan, Chen Yong, Cao Ji-hong, Jian Shui-shengAbstract:A novel scheme of all-optical Clock Recovery from mutiwavelength non-return-to-zero (NRZ) data stream is proposed and demonstrated. The chirp induced by a chirped fibre Bragg grating and a semiconductor optical amplifier is used to enhance the Clock. The Clock is recovered after injecting the enhanced signal into the scheme based on the stimulated Brillouin scattering. The experiment is carried out and the dual-wavelength Clock is recovered. This novel scheme can realize Clock Recovery of multiwavelength NRZ signal in the total wavelength range of 3.3 nm. This Clock Recovery technology is transparent to the data bit rate and modulation format, also without pattern dependence.
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Clock Recovery from CSRZ Based on Stimulated Brillouin Stattering
Journal of Optoelectronics·laser, 2007Co-Authors: Jian Shui-shengAbstract:A numerical model is built to analyze the carrier-suppressed return-to-zero(CSRZ)Clock Recovery system based on stimulated Brillouin scattering(SBS).The power conversion and interaction between the pumpand the seeds light is researched by using this model.The simulation results show that the power of the recovered Clock is affected by the length of dispersion shift fiber(DSF)and the ratio of the coupler.The optimized results exist.The experiment of 10 Gb/s CSRZ all optical Clock Recovery is demonstrated.The results are in good agreement with the theoretical predictions.
R.l. Aguiar - One of the best experts on this subject based on the ideXlab platform.
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Resource constrained Clock Recovery on programmable logic devices
9th International Conference on Electronics Circuits and Systems, 1Co-Authors: R.l. Aguiar, M. FigueiredoAbstract:Clock Recovery is an important task in communications. With the usage of programmable logic devices as core elements in communication systems, the integration of Clock Recovery in programmable logic devices (PLDs) is highly desirable. This paper discusses some facilities being provided in recent families of PLDs for timing management, and shows new architectures oriented for the implementation of Clock Recovery circuits for high-speed communications using these facilities, in such a resource constrained environment. In particular, a 155 Mbps Clock Recovery unit using low cost Xilinx devices is discussed, and its performance is compared with more traditional methods.
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ICECS - Resource constrained Clock Recovery on programmable logic devices
9th International Conference on Electronics Circuits and Systems, 1Co-Authors: R.l. Aguiar, M. FigueiredoAbstract:Clock Recovery is an important task in communications. With the usage of programmable logic devices as core elements in communication systems, the integration of Clock Recovery in programmable logic devices (PLDs) is highly desirable. This paper discusses some facilities being provided in recent families of PLDs for timing management, and shows new architectures oriented for the implementation of Clock Recovery circuits for high-speed communications using these facilities, in such a resource constrained environment. In particular, a 155 Mbps Clock Recovery unit using low cost Xilinx devices is discussed, and its performance is compared with more traditional methods.