The Experts below are selected from a list of 300 Experts worldwide ranked by ideXlab platform

Y Torroja - One of the best experts on this subject based on the ideXlab platform.

  • PATMOS - A method for switching activity analysis of VHDL-RTL Combinatorial Circuits
    Lecture Notes in Computer Science, 2006
    Co-Authors: Felipe Machado, Teresa Riesgo, Y Torroja
    Abstract:

    The analysis of circuit switching activity is a fundamental step towards dynamic power estimation of CMOS digital Circuits. In this paper, a probabilistic method for switching activity estimation of VHDL-RTL Combinatorial designs is presented. Switching activity estimation is performed through the propagation of input signals probabilities and switching activities by means of BDDs (Binary Decision Diagrams). In order to avoid the BDD memory explosion of large Circuits, an automatic circuit partition is performed taking advantage of the specific characteristics of some VHDL statements that permit the circuit division in exclusive regions. In addition, a reduced representation of switching activity BDDs is proposed. The method is implemented in a CAD tool, which, besides the signal probabilities and switching activities, offers abundant information and means for circuit exploration.

  • a method for switching activity analysis of vhdl rtl Combinatorial Circuits
    Lecture Notes in Computer Science, 2006
    Co-Authors: Felipe Machado, Teresa Riesgo, Y Torroja
    Abstract:

    The analysis of circuit switching activity is a fundamental step towards dynamic power estimation of CMOS digital Circuits. In this paper, a probabilistic method for switching activity estimation of VHDL-RTL Combinatorial designs is presented. Switching activity estimation is performed through the propagation of input signals probabilities and switching activities by means of BDDs (Binary Decision Diagrams). In order to avoid the BDD memory explosion of large Circuits, an automatic circuit partition is performed taking advantage of the specific characteristics of some VHDL statements that permit the circuit division in exclusive regions. In addition, a reduced representation of switching activity BDDs is proposed. The method is implemented in a CAD tool, which, besides the signal probabilities and switching activities, offers abundant information and means for circuit exploration.

Jan Schat - One of the best experts on this subject based on the ideXlab platform.

  • On the relationship between stuck-at fault coverage and transition fault coverage
    2009 Design Automation & Test in Europe Conference & Exhibition, 2009
    Co-Authors: Jan Schat
    Abstract:

    The single stuck-at fault coverage is often seen as a figure-of-merit also for scan testing according to other fault models like transition faults, bridging faults, crosstalk faults, etc. This paper analyzes how far this assumption is justified. Since the scan test infrastructure allows reaching states not reachable in the application mode, and since faults only detectable in such unreachable states are not relevant in the application mode, we distinguish those irrelevant faults from relevant faults, i.e. faults detectable in the application mode. We prove that every Combinatorial circuit with exactly 100% stuck-at fault coverage has 100% transition fault test coverage for those faults which are relevant in the application. This does not necessarily imply that Combinatorial Circuits with almost 100% single-stuck at coverage automatically have high transition fault coverage. This is shown in an extreme example of a circuit with nearly 100% stuck-at coverage, but 0% transition fault coverage.

  • DATE - On the relationship between stuck-at fault coverage and transition fault coverage
    2009 Design Automation & Test in Europe Conference & Exhibition, 2009
    Co-Authors: Jan Schat
    Abstract:

    The single stuck-at fault coverage is often seen as a figure-of-merit also for scan testing according to other fault models like transition faults, bridging faults, crosstalk faults, etc. This paper analyzes how far this assumption is justified. Since the scan test infrastructure allows reaching states not reachable in the application mode, and since faults only detectable in such unreachable states are not relevant in the application mode, we distinguish those irrelevant faults from relevant faults, i.e. faults detectable in the application mode. We prove that every Combinatorial circuit with exactly 100% stuck-at fault coverage has 100% transition fault test coverage for those faults which are relevant in the application. This does not necessarily imply that Combinatorial Circuits with almost 100% single-stuckat coverage automatically have high transition fault coverage. This is shown in an extreme example of a circuit with nearly 100% stuck-at coverage, but 0% transition fault coverage.

Felipe Machado - One of the best experts on this subject based on the ideXlab platform.

  • PATMOS - A method for switching activity analysis of VHDL-RTL Combinatorial Circuits
    Lecture Notes in Computer Science, 2006
    Co-Authors: Felipe Machado, Teresa Riesgo, Y Torroja
    Abstract:

    The analysis of circuit switching activity is a fundamental step towards dynamic power estimation of CMOS digital Circuits. In this paper, a probabilistic method for switching activity estimation of VHDL-RTL Combinatorial designs is presented. Switching activity estimation is performed through the propagation of input signals probabilities and switching activities by means of BDDs (Binary Decision Diagrams). In order to avoid the BDD memory explosion of large Circuits, an automatic circuit partition is performed taking advantage of the specific characteristics of some VHDL statements that permit the circuit division in exclusive regions. In addition, a reduced representation of switching activity BDDs is proposed. The method is implemented in a CAD tool, which, besides the signal probabilities and switching activities, offers abundant information and means for circuit exploration.

  • a method for switching activity analysis of vhdl rtl Combinatorial Circuits
    Lecture Notes in Computer Science, 2006
    Co-Authors: Felipe Machado, Teresa Riesgo, Y Torroja
    Abstract:

    The analysis of circuit switching activity is a fundamental step towards dynamic power estimation of CMOS digital Circuits. In this paper, a probabilistic method for switching activity estimation of VHDL-RTL Combinatorial designs is presented. Switching activity estimation is performed through the propagation of input signals probabilities and switching activities by means of BDDs (Binary Decision Diagrams). In order to avoid the BDD memory explosion of large Circuits, an automatic circuit partition is performed taking advantage of the specific characteristics of some VHDL statements that permit the circuit division in exclusive regions. In addition, a reduced representation of switching activity BDDs is proposed. The method is implemented in a CAD tool, which, besides the signal probabilities and switching activities, offers abundant information and means for circuit exploration.

K Subramani - One of the best experts on this subject based on the ideXlab platform.

  • Clustering without replication in Combinatorial Circuits
    Journal of Combinatorial Optimization, 2019
    Co-Authors: Zola Donovan, Vahan Mkrtchyan, Gregory Gutin, K Subramani
    Abstract:

    The modern integrated circuit is one of the most complex products engineered to date. It continues to grow in complexity as years progress. As a result, very large-scale integrated (VLSI) circuit design now involves massive design teams employing state-of-the-art computer-aided design (CAD) tools. One of the oldest, yet most important CAD problems for VLSI Circuits is physical design automation, where one needs to compute the best physical layout of millions to billions of circuit components on a tiny silicon surface (Lim in Practical problems in VLSI physical design automation, Springer, Dordrecht, 2008 ). The process of mapping an electronic design to a chip involves several physical design stages, one of which is clustering. Even for Combinatorial Circuits, there exists several models for the clustering problem. In particular, we consider the problem of clustering in Combinatorial Circuits for delay minimization, without permitting logic replication ( CN ). The problem of clustering for delay minimization when logic replication is allowed ( CA ) has been well-studied and is known to be solvable in polynomial time (Lawler et al. in IEEE Trans Comput 18(1):47–57, 1969 ; Rajaraman and Wong, in: 30th ACM/IEEE design automation conference, pp 309–314, 1993 ). However, unbounded logic replication can be quite expensive. It follows that CN is an important problem. We show that selected variants of CN are NP-hard . We also obtain approximability and inapproximability results for some of these problems. A preliminary version of this paper appears in Donovan et al. (in: 9th International conference on Combinatorial optimization and applications, COCOA 2015, Proceedings, pp 334–347, 2015 ).

  • disjoint clustering in Combinatorial Circuits
    International Workshop on Combinatorial Algorithms, 2019
    Co-Authors: Zola Donovan, K Subramani, Vahan Mkrtchyan
    Abstract:

    As the modern integrated circuit continues to grow in complexity, the design of very large-scale integrated (VLSI) Circuits involves massive teams employing state-of-the-art computer-aided design (CAD) tools. An old, yet significant CAD problem for VLSI Circuits is physical design automation. In this problem, one needs to compute the best physical layout of millions to billions of circuit components on a tiny silicon surface. The process of mapping an electronic design to a chip involves several physical design stages, one of which is clustering. Even for Combinatorial Circuits, there exists several models for the clustering problem. In particular, our primary consideration is the problem of disjoint clustering in Combinatorial Circuits for delay minimization (CN). The problem of clustering with replication for delay minimization has been well-studied and known to be solvable in polynomial time. However, replication can become expensive when it is unbounded. Consequently, CN is a problem worth investigating. We establish the computational complexities of several variants of CN. We also present a 2-approximation algorithm for an NP-hard variant of CN.

  • IWOCA - Disjoint Clustering in Combinatorial Circuits.
    Lecture Notes in Computer Science, 2019
    Co-Authors: Zola Donovan, K Subramani, Vahan Mkrtchyan
    Abstract:

    As the modern integrated circuit continues to grow in complexity, the design of very large-scale integrated (VLSI) Circuits involves massive teams employing state-of-the-art computer-aided design (CAD) tools. An old, yet significant CAD problem for VLSI Circuits is physical design automation. In this problem, one needs to compute the best physical layout of millions to billions of circuit components on a tiny silicon surface. The process of mapping an electronic design to a chip involves several physical design stages, one of which is clustering. Even for Combinatorial Circuits, there exists several models for the clustering problem. In particular, our primary consideration is the problem of disjoint clustering in Combinatorial Circuits for delay minimization (CN). The problem of clustering with replication for delay minimization has been well-studied and known to be solvable in polynomial time. However, replication can become expensive when it is unbounded. Consequently, CN is a problem worth investigating. We establish the computational complexities of several variants of CN. We also present a 2-approximation algorithm for an NP-hard variant of CN.

  • on clustering without replication in Combinatorial Circuits
    Conference on Combinatorial Optimization and Applications, 2015
    Co-Authors: Zola Donovan, Vahan Mkrtchyan, K Subramani
    Abstract:

    In this paper, we consider the problem of clustering Combinatorial Circuits for delay minimization, when logic replication is not allowed CN. The problem of delay minimization when logic replication is allowed CA has been well studied, and is known to be solvable in polynomial-time [8]. However, unbounded logic replication can be quite expensive. Thus, CN is an important problem. We show that selected variants of CN are NP-hard. We also obtain approximability and inapproximability results for these problems.

  • COCOA - On Clustering Without Replication in Combinatorial Circuits
    Combinatorial Optimization and Applications, 2015
    Co-Authors: Zola Donovan, Vahan Mkrtchyan, K Subramani
    Abstract:

    In this paper, we consider the problem of clustering Combinatorial Circuits for delay minimization, when logic replication is not allowed CN. The problem of delay minimization when logic replication is allowed CA has been well studied, and is known to be solvable in polynomial-time [8]. However, unbounded logic replication can be quite expensive. Thus, CN is an important problem. We show that selected variants of CN are NP-hard. We also obtain approximability and inapproximability results for these problems.

Teresa Riesgo - One of the best experts on this subject based on the ideXlab platform.

  • PATMOS - A method for switching activity analysis of VHDL-RTL Combinatorial Circuits
    Lecture Notes in Computer Science, 2006
    Co-Authors: Felipe Machado, Teresa Riesgo, Y Torroja
    Abstract:

    The analysis of circuit switching activity is a fundamental step towards dynamic power estimation of CMOS digital Circuits. In this paper, a probabilistic method for switching activity estimation of VHDL-RTL Combinatorial designs is presented. Switching activity estimation is performed through the propagation of input signals probabilities and switching activities by means of BDDs (Binary Decision Diagrams). In order to avoid the BDD memory explosion of large Circuits, an automatic circuit partition is performed taking advantage of the specific characteristics of some VHDL statements that permit the circuit division in exclusive regions. In addition, a reduced representation of switching activity BDDs is proposed. The method is implemented in a CAD tool, which, besides the signal probabilities and switching activities, offers abundant information and means for circuit exploration.

  • a method for switching activity analysis of vhdl rtl Combinatorial Circuits
    Lecture Notes in Computer Science, 2006
    Co-Authors: Felipe Machado, Teresa Riesgo, Y Torroja
    Abstract:

    The analysis of circuit switching activity is a fundamental step towards dynamic power estimation of CMOS digital Circuits. In this paper, a probabilistic method for switching activity estimation of VHDL-RTL Combinatorial designs is presented. Switching activity estimation is performed through the propagation of input signals probabilities and switching activities by means of BDDs (Binary Decision Diagrams). In order to avoid the BDD memory explosion of large Circuits, an automatic circuit partition is performed taking advantage of the specific characteristics of some VHDL statements that permit the circuit division in exclusive regions. In addition, a reduced representation of switching activity BDDs is proposed. The method is implemented in a CAD tool, which, besides the signal probabilities and switching activities, offers abundant information and means for circuit exploration.