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K S Sunil - One of the best experts on this subject based on the ideXlab platform.
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Comparator Circuits over finite bounded posets
Information & Computation, 2018Co-Authors: Balagopal Komarath, Jayalal Sarma, K S SunilAbstract:Abstract The Comparator circuit model was originally introduced by Mayr et al. (1992) (and further studied by Cook et al. (2014)) to capture problems that are not known to be P -complete but still not known to admit efficient parallel algorithms. The class CC is the complexity class of problems many-one logspace reducible to the Comparator Circuit Value Problem and we know that NLOG ⊆ CC ⊆ P . Cook et al. (2014) showed that CC is also the class of languages decided by polynomial size Comparator circuit families. We study generalizations of the Comparator circuit model that work over fixed finite bounded posets. We observe that there are universal Comparator Circuits even over arbitrary fixed finite bounded posets. Building on this, we show the following: • Comparator Circuits of polynomial size over fixed finite distributive lattices characterize the class CC . When the circuit is restricted to be skew, they characterize LOG . Noting that (uniform) polynomial sized Boolean Circuits (resp. skew) characterize P (resp. NLOG ), this indicates a comparison between P vs CC and NLOG vs LOG problems. • Complementing this, we show that Comparator Circuits of polynomial size over arbitrary fixed finite lattices characterize the class P even when the Comparator circuit is skew. • In addition, we show a characterization of the class NP by a family of polynomial sized Comparator Circuits over fixed finite bounded posets . As an aside, we consider generalizations of Boolean formulae over arbitrary lattices. We show that Spira's theorem (Spira, 1971) can be extended to this setting as well and show that polynomial sized Boolean formulae over finite fixed lattices capture the class NC 1 . These results generalize results in Cook et al. (2014) regarding the power of Comparator Circuits. Our techniques involve design of Comparator Circuits and finite posets. We then use known results from lattice theory to show that the posets that we obtain can be embedded into appropriate lattices. Our results give new methods to establish CC upper bounds for problems and also indicate potential new approaches towards the problems P vs CC and NLOG vs LOG using lattice theoretic methods.
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Comparator Circuits over finite bounded posets
International Colloquium on Automata Languages and Programming, 2015Co-Authors: Balagopal Komarath, Jayalal Sarma, K S SunilAbstract:Comparator circuit model was originally introduced in [4] (and further studied in [2]) to capture problems which are not known to be P-complete but still not known to admit efficient parallel algorithms. The class CC is the complexity class of problems many-one logspace reducible to the Comparator Circuit Value Problem and we know that NLOG \(\subseteq \) CC \(\subseteq \) P. Cook et al [2] showed that CC is also the class of languages decided by polynomial size Comparator Circuits.
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Comparator Circuits over finite bounded posets
arXiv: Computational Complexity, 2015Co-Authors: Balagopal Komarath, Jayalal Sarma, K S SunilAbstract:Comparator circuit model was originally introduced by Mayr and Subramanian (1992) (and further studied by Cook, Filmus and Le (2012)) to capture problems which are not known to be P-complete but still not known to admit efficient parallel algorithms. The class CC is the complexity class of problems many-one logspace reducible to the Comparator Circuit Value Problem and we know that NL is contained in CC which is inturn contained in P. Cook, Filmus and Le (2012) showed that CC is also the class of languages decided by polynomial size Comparator Circuits. We study generalizations of the Comparator circuit model that work over fixed finite bounded posets. We observe that there are universal Comparator Circuits even over arbitrary fixed finite bounded posets. Building on this, we show that general (resp. skew) Comparator Circuits of polynomial size over fixed finite distributive lattices characterizes CC (resp. L). Complementing this, we show that general Comparator Circuits of polynomial size over arbitrary fixed finite lattices exactly characterizes P even when the Comparator circuit is skew. In addition, we show a characterization of the class NP by a family of polynomial sized Comparator Circuits over fixed {\em finite bounded posets}. These results generalize the results by Cook, Filmus and Le (2012) regarding the power of Comparator Circuits. As an aside, we consider generalizations of Boolean formulae over arbitrary lattices. We show that Spira's theorem (1971) can be extended to this setting as well and show that polynomial sized Boolean formulae over finite fixed lattices capture exactly NC^1.
Balagopal Komarath - One of the best experts on this subject based on the ideXlab platform.
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Comparator Circuits over finite bounded posets
Information & Computation, 2018Co-Authors: Balagopal Komarath, Jayalal Sarma, K S SunilAbstract:Abstract The Comparator circuit model was originally introduced by Mayr et al. (1992) (and further studied by Cook et al. (2014)) to capture problems that are not known to be P -complete but still not known to admit efficient parallel algorithms. The class CC is the complexity class of problems many-one logspace reducible to the Comparator Circuit Value Problem and we know that NLOG ⊆ CC ⊆ P . Cook et al. (2014) showed that CC is also the class of languages decided by polynomial size Comparator circuit families. We study generalizations of the Comparator circuit model that work over fixed finite bounded posets. We observe that there are universal Comparator Circuits even over arbitrary fixed finite bounded posets. Building on this, we show the following: • Comparator Circuits of polynomial size over fixed finite distributive lattices characterize the class CC . When the circuit is restricted to be skew, they characterize LOG . Noting that (uniform) polynomial sized Boolean Circuits (resp. skew) characterize P (resp. NLOG ), this indicates a comparison between P vs CC and NLOG vs LOG problems. • Complementing this, we show that Comparator Circuits of polynomial size over arbitrary fixed finite lattices characterize the class P even when the Comparator circuit is skew. • In addition, we show a characterization of the class NP by a family of polynomial sized Comparator Circuits over fixed finite bounded posets . As an aside, we consider generalizations of Boolean formulae over arbitrary lattices. We show that Spira's theorem (Spira, 1971) can be extended to this setting as well and show that polynomial sized Boolean formulae over finite fixed lattices capture the class NC 1 . These results generalize results in Cook et al. (2014) regarding the power of Comparator Circuits. Our techniques involve design of Comparator Circuits and finite posets. We then use known results from lattice theory to show that the posets that we obtain can be embedded into appropriate lattices. Our results give new methods to establish CC upper bounds for problems and also indicate potential new approaches towards the problems P vs CC and NLOG vs LOG using lattice theoretic methods.
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Comparator Circuits over finite bounded posets
International Colloquium on Automata Languages and Programming, 2015Co-Authors: Balagopal Komarath, Jayalal Sarma, K S SunilAbstract:Comparator circuit model was originally introduced in [4] (and further studied in [2]) to capture problems which are not known to be P-complete but still not known to admit efficient parallel algorithms. The class CC is the complexity class of problems many-one logspace reducible to the Comparator Circuit Value Problem and we know that NLOG \(\subseteq \) CC \(\subseteq \) P. Cook et al [2] showed that CC is also the class of languages decided by polynomial size Comparator Circuits.
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Comparator Circuits over finite bounded posets
arXiv: Computational Complexity, 2015Co-Authors: Balagopal Komarath, Jayalal Sarma, K S SunilAbstract:Comparator circuit model was originally introduced by Mayr and Subramanian (1992) (and further studied by Cook, Filmus and Le (2012)) to capture problems which are not known to be P-complete but still not known to admit efficient parallel algorithms. The class CC is the complexity class of problems many-one logspace reducible to the Comparator Circuit Value Problem and we know that NL is contained in CC which is inturn contained in P. Cook, Filmus and Le (2012) showed that CC is also the class of languages decided by polynomial size Comparator Circuits. We study generalizations of the Comparator circuit model that work over fixed finite bounded posets. We observe that there are universal Comparator Circuits even over arbitrary fixed finite bounded posets. Building on this, we show that general (resp. skew) Comparator Circuits of polynomial size over fixed finite distributive lattices characterizes CC (resp. L). Complementing this, we show that general Comparator Circuits of polynomial size over arbitrary fixed finite lattices exactly characterizes P even when the Comparator circuit is skew. In addition, we show a characterization of the class NP by a family of polynomial sized Comparator Circuits over fixed {\em finite bounded posets}. These results generalize the results by Cook, Filmus and Le (2012) regarding the power of Comparator Circuits. As an aside, we consider generalizations of Boolean formulae over arbitrary lattices. We show that Spira's theorem (1971) can be extended to this setting as well and show that polynomial sized Boolean formulae over finite fixed lattices capture exactly NC^1.
Jayalal Sarma - One of the best experts on this subject based on the ideXlab platform.
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Comparator Circuits over finite bounded posets
Information & Computation, 2018Co-Authors: Balagopal Komarath, Jayalal Sarma, K S SunilAbstract:Abstract The Comparator circuit model was originally introduced by Mayr et al. (1992) (and further studied by Cook et al. (2014)) to capture problems that are not known to be P -complete but still not known to admit efficient parallel algorithms. The class CC is the complexity class of problems many-one logspace reducible to the Comparator Circuit Value Problem and we know that NLOG ⊆ CC ⊆ P . Cook et al. (2014) showed that CC is also the class of languages decided by polynomial size Comparator circuit families. We study generalizations of the Comparator circuit model that work over fixed finite bounded posets. We observe that there are universal Comparator Circuits even over arbitrary fixed finite bounded posets. Building on this, we show the following: • Comparator Circuits of polynomial size over fixed finite distributive lattices characterize the class CC . When the circuit is restricted to be skew, they characterize LOG . Noting that (uniform) polynomial sized Boolean Circuits (resp. skew) characterize P (resp. NLOG ), this indicates a comparison between P vs CC and NLOG vs LOG problems. • Complementing this, we show that Comparator Circuits of polynomial size over arbitrary fixed finite lattices characterize the class P even when the Comparator circuit is skew. • In addition, we show a characterization of the class NP by a family of polynomial sized Comparator Circuits over fixed finite bounded posets . As an aside, we consider generalizations of Boolean formulae over arbitrary lattices. We show that Spira's theorem (Spira, 1971) can be extended to this setting as well and show that polynomial sized Boolean formulae over finite fixed lattices capture the class NC 1 . These results generalize results in Cook et al. (2014) regarding the power of Comparator Circuits. Our techniques involve design of Comparator Circuits and finite posets. We then use known results from lattice theory to show that the posets that we obtain can be embedded into appropriate lattices. Our results give new methods to establish CC upper bounds for problems and also indicate potential new approaches towards the problems P vs CC and NLOG vs LOG using lattice theoretic methods.
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Comparator Circuits over finite bounded posets
International Colloquium on Automata Languages and Programming, 2015Co-Authors: Balagopal Komarath, Jayalal Sarma, K S SunilAbstract:Comparator circuit model was originally introduced in [4] (and further studied in [2]) to capture problems which are not known to be P-complete but still not known to admit efficient parallel algorithms. The class CC is the complexity class of problems many-one logspace reducible to the Comparator Circuit Value Problem and we know that NLOG \(\subseteq \) CC \(\subseteq \) P. Cook et al [2] showed that CC is also the class of languages decided by polynomial size Comparator Circuits.
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Comparator Circuits over finite bounded posets
arXiv: Computational Complexity, 2015Co-Authors: Balagopal Komarath, Jayalal Sarma, K S SunilAbstract:Comparator circuit model was originally introduced by Mayr and Subramanian (1992) (and further studied by Cook, Filmus and Le (2012)) to capture problems which are not known to be P-complete but still not known to admit efficient parallel algorithms. The class CC is the complexity class of problems many-one logspace reducible to the Comparator Circuit Value Problem and we know that NL is contained in CC which is inturn contained in P. Cook, Filmus and Le (2012) showed that CC is also the class of languages decided by polynomial size Comparator Circuits. We study generalizations of the Comparator circuit model that work over fixed finite bounded posets. We observe that there are universal Comparator Circuits even over arbitrary fixed finite bounded posets. Building on this, we show that general (resp. skew) Comparator Circuits of polynomial size over fixed finite distributive lattices characterizes CC (resp. L). Complementing this, we show that general Comparator Circuits of polynomial size over arbitrary fixed finite lattices exactly characterizes P even when the Comparator circuit is skew. In addition, we show a characterization of the class NP by a family of polynomial sized Comparator Circuits over fixed {\em finite bounded posets}. These results generalize the results by Cook, Filmus and Le (2012) regarding the power of Comparator Circuits. As an aside, we consider generalizations of Boolean formulae over arbitrary lattices. We show that Spira's theorem (1971) can be extended to this setting as well and show that polynomial sized Boolean formulae over finite fixed lattices capture exactly NC^1.
L Selmi - One of the best experts on this subject based on the ideXlab platform.
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understanding the potential and limitations of tunnel fets for low voltage analog mixed signal Circuits
IEEE Transactions on Electron Devices, 2017Co-Authors: Francesco Settino, Marco Lanuzza, Sebastiano Strangio, F Crupi, P Palestri, D Esseni, L SelmiAbstract:In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node. The advantages and limits of TFETs over their FinFET counterparts are discussed in detail, considering the main analog figures of merits, as well as the implementation of low-voltage track-and-hold (T/H) and Comparator Circuits. It is found that the higher output resistance offered by TFET-based designs allows achieving significantly higher intrinsic voltage gain and higher maximum-oscillation frequency at low current levels. TFET-based T/H Circuits have better accuracy and better hold performance by using the dummy switch solution for the mitigation of the charge injection. Among the Comparator Circuits, the TFET-based conventional dynamic architecture exhibits the best performance while keeping lower area occupation with respect to the more complex double-tail Circuits. Moreover, it outperforms all the FinFET counterparts over a wide range of supply voltage when considering low values of the common-mode voltage.
Francesco Settino - One of the best experts on this subject based on the ideXlab platform.
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understanding the potential and limitations of tunnel fets for low voltage analog mixed signal Circuits
IEEE Transactions on Electron Devices, 2017Co-Authors: Francesco Settino, Marco Lanuzza, Sebastiano Strangio, F Crupi, P Palestri, D Esseni, L SelmiAbstract:In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node. The advantages and limits of TFETs over their FinFET counterparts are discussed in detail, considering the main analog figures of merits, as well as the implementation of low-voltage track-and-hold (T/H) and Comparator Circuits. It is found that the higher output resistance offered by TFET-based designs allows achieving significantly higher intrinsic voltage gain and higher maximum-oscillation frequency at low current levels. TFET-based T/H Circuits have better accuracy and better hold performance by using the dummy switch solution for the mitigation of the charge injection. Among the Comparator Circuits, the TFET-based conventional dynamic architecture exhibits the best performance while keeping lower area occupation with respect to the more complex double-tail Circuits. Moreover, it outperforms all the FinFET counterparts over a wide range of supply voltage when considering low values of the common-mode voltage.