The Experts below are selected from a list of 43203 Experts worldwide ranked by ideXlab platform
Unku Moo - One of the best experts on this subject based on the ideXlab platform.
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stochastic flash analog to digital conversion
IEEE Transactions on Circuits and Systems, 2010Co-Authors: Skyle Weave, Enjami Hershberg, P Kurahashi, D Knierim, Unku MooAbstract:A stochastic flash analog-to-digital converter (ADC) is presented. A standard flash uses a resistor string to set individual Comparator trip points. A stochastic flash ADC uses random Comparator offset to set the trip points. Since the Comparators are no longer sized for small offset, they can be shrunk down into digital cells. Using Comparators that are implemented as digital cells produces a large variation of Comparator offset. Typically, this is considered a disadvantage, but in our case, this large standard deviation of offset is used to set the input signal range. By designing an ADC that is made up entirely of digital cells, it is a natural candidate for a synthesizable ADC. Comparator trip points follow the nonlinear transfer function described by a Gaussian cumulative distribution function, and a technique is presented that reduces this nonlinearity by changing the overall transfer function of the stochastic flash ADC. A test chip is fabricated in 0.18- CMOS to demonstrate the concept.
Barosaim Sung - One of the best experts on this subject based on the ideXlab platform.
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a 6 b 4 1 gs s flash adc with time domain latch interpolation in 90 nm cmos
IEEE Journal of Solid-state Circuits, 2013Co-Authors: Barosaim SungAbstract:A 6-b 4.1-GS/s flash ADC was fabricated using a 90-nm CMOS with a time-domain latch interpolation technique that reduces the number of front-end dynamic Comparators by half. The reduced number of Comparators lowers power consumption, load capacitance to the T/H circuit, and the overhead of Comparator calibration. The measured peak INL and DNL after Comparator calibration are 0.74 and 0.49 LSB, respectively. The measured SNDR and SFDR are 31.2 and 38.3 dB, respectively, with a 2.02-GHz input at 4.1-GS/s operation while consuming 76 mW of total power. This ADC achieves a figure of merit of 0.625 pJ/conversion-step at 4.1 GS/s.
Min-ki Jeon - One of the best experts on this subject based on the ideXlab platform.
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A Stochastic Flash Analog-to-Digital Converter Linearized by Reference Swapping
IEEE Access, 2017Co-Authors: Min-ki JeonAbstract:The linearity of a stochastic flash analog-to-digital converter (ADC) with two groups of Comparators is improved by reference swapping. If the input offset of a Comparator is larger than the linear input range of its Comparator group, the reference voltage of the Comparator is swapped with the reference voltage of the other Comparator group. The reference swapping doubles the number of Comparators providing a meaningful result in determining the ADC output. A stochastic flash ADC linearized by the reference swapping has been implemented in a 65-nm CMOS process. The peak signal-to-noise + distortion ratio is 39 dB, which is 3-dB higher than that without the reference swapping.
Behzad Razavi - One of the best experts on this subject based on the ideXlab platform.
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the design of a Comparator the analog mind
IEEE Solid-State Circuits Magazine, 2020Co-Authors: Behzad RazaviAbstract:Nyquist-rate and oversampling analog- to-digital converters (ADCs) incorporate Comparators to perform quantization and possibly sampling. Comparators thus have a significant impact on the speed and precision of ADCs. This article presents the step-by-step design of a Comparator and the discovery of its various trade-offs.
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design techniques for high speed high resolution Comparators
IEEE Journal of Solid-state Circuits, 1992Co-Authors: Behzad Razavi, B A WooleyAbstract:Precision techniques for the design of Comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described. Following a review of conventional offset cancellation techniques, circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented. The BiCMOS Comparator consists of a preamplifier followed by two regenerative stages and achieves an offset of 200 mu V at a 10-MHz clock rate while dissipating 1.7 mW. In the CMOS Comparator offset cancellation is used in both a single-stage preamplifier and a subsequent latch to achieve an offset of less than 300 mu V at comparison rates as high as 10 MHz, with a power dissipation of 1.8 mW. >
Skyle Weave - One of the best experts on this subject based on the ideXlab platform.
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stochastic flash analog to digital conversion
IEEE Transactions on Circuits and Systems, 2010Co-Authors: Skyle Weave, Enjami Hershberg, P Kurahashi, D Knierim, Unku MooAbstract:A stochastic flash analog-to-digital converter (ADC) is presented. A standard flash uses a resistor string to set individual Comparator trip points. A stochastic flash ADC uses random Comparator offset to set the trip points. Since the Comparators are no longer sized for small offset, they can be shrunk down into digital cells. Using Comparators that are implemented as digital cells produces a large variation of Comparator offset. Typically, this is considered a disadvantage, but in our case, this large standard deviation of offset is used to set the input signal range. By designing an ADC that is made up entirely of digital cells, it is a natural candidate for a synthesizable ADC. Comparator trip points follow the nonlinear transfer function described by a Gaussian cumulative distribution function, and a technique is presented that reduces this nonlinearity by changing the overall transfer function of the stochastic flash ADC. A test chip is fabricated in 0.18- CMOS to demonstrate the concept.
