The Experts below are selected from a list of 15693 Experts worldwide ranked by ideXlab platform
Steve Collins - One of the best experts on this subject based on the ideXlab platform.
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An integrating wide dynamic range nMOS pixel with a logarithmic Reference Voltage generator
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016Co-Authors: Mus'ab Shaharom, Steve CollinsAbstract:An all nMOS image sensor with a wide dynamic range (WDR) response has been designed. In particular an improve d scheme to obtain a user-controlled logarithmic response with a 120 dB dynamic range from an integrating pixel is described. This scheme requires a time modulated input Reference to the pixel and a method to generate this Reference Voltage on chip is proposed as an alternative to previous off-chip Voltage generating solutions. An array of 256×256 of 5×5 μm2 pixels and the Reference Voltage generator have been fabricated using a 180 nm 1P6M CMOS process.
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ISCAS - An integrating wide dynamic range nMOS pixel with a logarithmic Reference Voltage generator
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016Co-Authors: Mus'ab Shaharom, Steve CollinsAbstract:An all nMOS image sensor with a wide dynamic range (WDR) response has been designed. In particular an improve d scheme to obtain a user-controlled logarithmic response with a 120 dB dynamic range from an integrating pixel is described. This scheme requires a time modulated input Reference to the pixel and a method to generate this Reference Voltage on chip is proposed as an alternative to previous off-chip Voltage generating solutions. An array of 256×256 of 5×5 μm2 pixels and the Reference Voltage generator have been fabricated using a 180 nm 1P6M CMOS process.
Mus'ab Shaharom - One of the best experts on this subject based on the ideXlab platform.
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An integrating wide dynamic range nMOS pixel with a logarithmic Reference Voltage generator
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016Co-Authors: Mus'ab Shaharom, Steve CollinsAbstract:An all nMOS image sensor with a wide dynamic range (WDR) response has been designed. In particular an improve d scheme to obtain a user-controlled logarithmic response with a 120 dB dynamic range from an integrating pixel is described. This scheme requires a time modulated input Reference to the pixel and a method to generate this Reference Voltage on chip is proposed as an alternative to previous off-chip Voltage generating solutions. An array of 256×256 of 5×5 μm2 pixels and the Reference Voltage generator have been fabricated using a 180 nm 1P6M CMOS process.
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ISCAS - An integrating wide dynamic range nMOS pixel with a logarithmic Reference Voltage generator
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016Co-Authors: Mus'ab Shaharom, Steve CollinsAbstract:An all nMOS image sensor with a wide dynamic range (WDR) response has been designed. In particular an improve d scheme to obtain a user-controlled logarithmic response with a 120 dB dynamic range from an integrating pixel is described. This scheme requires a time modulated input Reference to the pixel and a method to generate this Reference Voltage on chip is proposed as an alternative to previous off-chip Voltage generating solutions. An array of 256×256 of 5×5 μm2 pixels and the Reference Voltage generator have been fabricated using a 180 nm 1P6M CMOS process.
Frederik De Belie - One of the best experts on this subject based on the ideXlab platform.
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Reference Voltage Vector Based Model Predictive Torque Control with RMS Solution for PMSM
2019 IEEE 28th International Symposium on Industrial Electronics (ISIE), 2019Co-Authors: Huayu Li, Frederik De BelieAbstract:To reduce the computational burden of a conventional model predictive torque controller (MPTC), a Reference Voltage vector based MPTC strategy is proposed. The Reference Voltage vector is obtained from the Reference stator flux vector and the Reference torque. According to the location of the Reference Voltage vector, a first optimal vector can be determined in a quite straightforward way, improving the system dynamic performance. Furthermore, in order to decrease the torque and flux ripple, a root mean square (RMS) based solution is employed to generate the Reference Voltage vector and calculate the duty ratio. This method aims at minimizing the RMS error of flux and torque during the whole control period. Then, the steady state performance is improved. Besides, since the new cost function contains only the Reference Voltage vector, the weighting factor in conventional MPTC is eliminated. In addition, to keep a balance between the steady state performance and switching frequency, the candidates for the second optimal vector are restricted to a certain scope. Simulations were carried out and the results verified the validation of the proposed MPTC strategy.
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ISIE - Reference Voltage Vector Based Model Predictive Torque Control with RMS Solution for PMSM
2019 IEEE 28th International Symposium on Industrial Electronics (ISIE), 2019Co-Authors: Chenwei Ma, Huayu Li, Frederik De BelieAbstract:To reduce the computational burden of a conventional model predictive torque controller (MPTC), a Reference Voltage vector based MPTC strategy is proposed. The Reference Voltage vector is obtained from the Reference stator flux vector and the Reference torque. According to the location of the Reference Voltage vector, a first optimal vector can be determined in a quite straightforward way, improving the system dynamic performance. Furthermore, in order to decrease the torque and flux ripple, a root mean square (RMS) based solution is employed to generate the Reference Voltage vector and calculate the duty ratio. This method aims at minimizing the RMS error of flux and torque during the whole control period. Then, the steady state performance is improved. Besides, since the new cost function contains only the Reference Voltage vector, the weighting factor in conventional MPTC is eliminated. In addition, to keep a balance between the steady state performance and switching frequency, the candidates for the second optimal vector are restricted to a certain scope. Simulations were carried out and the results verified the validation of the proposed MPTC strategy.
J. Jacob Wikner - One of the best experts on this subject based on the ideXlab platform.
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A 10-bit 50MS/s SAR ADC in 65nm CMOS with on-chip Reference Voltage buffer
Integration, 2015Co-Authors: Prakash Harikumar, J. Jacob WiknerAbstract:This paper presents the design of a 10-bit, 50MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip Reference Voltage buffer implemented in 65nm CMOS process. The speed limitation on SAR ADCs with off-chip Reference Voltage and the necessity of a fast-settling Reference Voltage buffer are elaborated. Design details of a high-speed Reference Voltage buffer which ensures precise settling of the DAC output Voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25bits at a supply Voltage of 1.2V, typical process corner and sampling frequency of 50MS/s for near-Nyquist input. Excluding the Reference Voltage buffer, the ADC consumes 697µW and achieves an energy efficiency of 25fJ/conversion-step while occupying a core area of 0.055mm2. HighlightsThe limitation posed by incomplete DAC settling in medium-to-high speed SAR ADCs is addressed.The design details of a high-speed Reference Voltage buffer (RVBuffer) are elaborated.Estimation of key performance parameters of the RV Buffer are provided.Post-layout simulation of the full ADC including device noise and IO pad parasitics has been reported.
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Design of a Reference Voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015Co-Authors: Prakash Harikumar, J. Jacob WiknerAbstract:This paper presents the design of a fast-settling Reference Voltage buffer (RVBuffer) which is used to buffer the high Reference Voltage in a 10-bit, 50 MS/s successive approximation register (SAR) ADC implemented in 65 nm CMOS. Though numerous publications on SAR ADCs have appeared in recent years, the role of RVBuffers in ensuring ADC performance, the associated design challenges and impact on power and FoM of the entire ADC have not been discussed in-depth. In this work, the speed limitation on precise settling of the digital-to-analog converter Voltage (DAC) in a SAR ADC imposed by parasitic inductances of the bondwire and PCB trace is explained. The crucial design parameters for the Reference Voltage buffer in the context of the SAR ADC are derived. Post-layout simulation results for the RVBuffer are provided to verify settling-time, noise and PSRR performance. In post-layout simulation which includes the entire pad frame and associated parasitics, the SAR ADC achieves an ENOB of 9.25 bits at a supply Voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the Reference Voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.
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ISCAS - Design of a Reference Voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015Co-Authors: Prakash Harikumar, J. Jacob WiknerAbstract:This paper presents the design of a fast-settling Reference Voltage buffer (RVBuffer) which is used to buffer the high Reference Voltage in a 10-bit, 50 MS/s successive approximation register (SAR) ADC implemented in 65 nm CMOS. Though numerous publications on SAR ADCs have appeared in recent years, the role of RVBuffers in ensuring ADC performance, the associated design challenges and impact on power and FoM of the entire ADC have not been discussed in-depth. In this work, the speed limitation on precise settling of the digital-to-analog converter Voltage (DAC) in a SAR ADC imposed by parasitic inductances of the bondwire and PCB trace is explained. The crucial design parameters for the Reference Voltage buffer in the context of the SAR ADC are derived. Post-layout simulation results for the RVBuffer are provided to verify settling-time, noise and PSRR performance. In post-layout simulation which includes the entire pad frame and associated parasitics, the SAR ADC achieves an ENOB of 9.25 bits at a supply Voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the Reference Voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.
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Design of a Reference Voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS
Proceedings - IEEE International Symposium on Circuits and Systems, 2015Co-Authors: Prakash Harikumar, J. Jacob WiknerAbstract:Abstract This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip Reference Voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip Reference Voltage and the necessity of a fast-settling Reference Voltage buffer are elaborated. Design details of a high-speed Reference Voltage buffer which ensures precise settling of the DAC output Voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply Voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the Reference Voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.
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A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip Reference Voltage buffer
Integration the VLSI Journal, 2015Co-Authors: Prakash Harikumar, J. Jacob WiknerAbstract:Abstract This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip Reference Voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip Reference Voltage and the necessity of a fast-settling Reference Voltage buffer are elaborated. Design details of a high-speed Reference Voltage buffer which ensures precise settling of the DAC output Voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply Voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the Reference Voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.
Yuantao Gu - One of the best experts on this subject based on the ideXlab platform.
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Quantization Reference Voltage of the Modulated Wideband Converter
2012 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP), 2012Co-Authors: Yaming Wang, Laming Chen, Yuantao GuAbstract:The Modulated Wideband Converter (MWC) is a recently proposed analog-to-digital converter (ADC) based on Compressive Sensing (CS) theory. Unlike conventional ADCs, its quantization Reference Voltage, which is important to the system performance, does not equal the maximum amplitude of original analog signal. In this paper, the quantization Reference Voltage of the MWC is theoretically analyzed and the conclusion demonstrates that the Reference Voltage is proportional to the square root of q, which is a trade-off parameter between sampling rate and number of channels. Further discussions and simulation results show that the Reference Voltage is proportional to the square root of Nq when the signal consists of N narrowband signals.
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ICASSP - Quantization Reference Voltage of the Modulated Wideband Converter
2012 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP), 2012Co-Authors: Yaming Wang, Laming Chen, Yuantao GuAbstract:The Modulated Wideband Converter (MWC) is a recently proposed analogv-to-digital converter (ADC) based on Compressive Sensing (CS) theory. Unlike conventional ADCs, its quantization Reference Voltage, which is important to the system performance, does not equal the maximum amplitude of original analog signal. In this paper, the quantization Reference Voltage of the MWC is theoretically analyzed and the conclusion demonstrates that the Reference Voltage is proportional to the square root of q, which is a trade-off parameter between sampling rate and number of channels. Further discussions and simulation results show that the Reference Voltage is proportional to the square root of Nq when the signal consists of N narrowband signals.
