The Experts below are selected from a list of 89202 Experts worldwide ranked by ideXlab platform
Stuart Pocock - One of the best experts on this subject based on the ideXlab platform.
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A Framework for Methodological Choice and Evidence Assessment for Studies Using External Comparators from Real-World Data
Drug Safety, 2020Co-Authors: Christen M. Gray, Fiona Grimson, Deborah Layton, Stuart PocockAbstract:Several approaches have been proposed recently to accelerate the pathway from drug discovery to patient access. These include novel designs such as using controls external to the clinical trial where standard randomised controls are not feasible. In parallel, there has been rapid growth in the application of routinely collected healthcare ‘real-world’ data for post-market safety and effectiveness studies. Thus, using real-world data to establish an external comparator arm in clinical trials is a natural next step. Regulatory authorities have begun to endorse the use of external Comparators in certain circumstances, with some positive outcomes for new drug approvals. Given the potential to introduce bias associated with observational studies, there is a need for recommendations on how external Comparators should be best used. In this article, we propose an evaluation framework for real-world data external comparator studies that enables full assessment of available evidence and related bias. We define the principle of exchangeability and discuss the applicability of criteria described by Pocock for consideration of the exchangeability of the external and trial populations. We explore how trial designs using real-world data external Comparators fit within the evidence hierarchy and propose a four-step process for good conduct of external comparator studies. This process is intended to maximise the quality of evidence based on careful study design and the combination of covariate balancing, bias analysis and combining outcomes.
Mingoo Seok - One of the best experts on this subject based on the ideXlab platform.
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comparative study and optimization of synchronous and asynchronous Comparators at near threshold voltages
International Symposium on Low Power Electronics and Design, 2017Co-Authors: Mingoo SeokAbstract:We optimize and compare the performance of synchronous and asynchronous Comparators across near-threshold and nominal supply voltage (0.5∼1V). Comparators are the key components that determine the fundamental performance of analog-to-digital conversion in control and digital-signal processing (DSP) systems. While the asynchronous comparator has been considered inferior, operation of transistors in the near-threshold regime grants asynchronous Comparators opportunities to improve power efficiency due to the more reduction in crowbar current than saturation drain current. We propose an enhanced asynchronous CSDA based comparator capable of achieving a superior latency vs. quiescent power dissipation trade-off to the synchronous clocked comparator in the near-threshold regime, a metric that is beneficial particularly to event-driven control systems. In-depth optimization and comparison results are presented.
Christen M. Gray - One of the best experts on this subject based on the ideXlab platform.
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A Framework for Methodological Choice and Evidence Assessment for Studies Using External Comparators from Real-World Data
Drug Safety, 2020Co-Authors: Christen M. Gray, Fiona Grimson, Deborah Layton, Stuart PocockAbstract:Several approaches have been proposed recently to accelerate the pathway from drug discovery to patient access. These include novel designs such as using controls external to the clinical trial where standard randomised controls are not feasible. In parallel, there has been rapid growth in the application of routinely collected healthcare ‘real-world’ data for post-market safety and effectiveness studies. Thus, using real-world data to establish an external comparator arm in clinical trials is a natural next step. Regulatory authorities have begun to endorse the use of external Comparators in certain circumstances, with some positive outcomes for new drug approvals. Given the potential to introduce bias associated with observational studies, there is a need for recommendations on how external Comparators should be best used. In this article, we propose an evaluation framework for real-world data external comparator studies that enables full assessment of available evidence and related bias. We define the principle of exchangeability and discuss the applicability of criteria described by Pocock for consideration of the exchangeability of the external and trial populations. We explore how trial designs using real-world data external Comparators fit within the evidence hierarchy and propose a four-step process for good conduct of external comparator studies. This process is intended to maximise the quality of evidence based on careful study design and the combination of covariate balancing, bias analysis and combining outcomes.
C J Madden - One of the best experts on this subject based on the ideXlab platform.
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simulation and analysis of random decision errors in clocked Comparators
Custom Integrated Circuits Conference, 2009Co-Authors: Brian S Leibowitz, C J MaddenAbstract:Clocked Comparators have found widespread use in noise sensitive applications including analog-to-digital converters, wireline receivers, and memory bit-line detectors. However, their nonlinear, time-varying dynamics resulting in discrete output levels have discouraged the use of traditional linear time-invariant (LTI) small-signal analysis and noise simulation techniques. This paper describes a linear, time-varying (LTV) model of clock Comparators that can accurately predict the decision error probability without resorting to more general stochastic system models. The LTV analysis framework in conjunction with the linear, periodically time-varying (LPTV) simulation algorithms available from RF circuit simulators can provide insights into the intrinsic sampling and decision operations of clock Comparators and the major contribution sources to random decision errors. Two Comparators are simulated and compared with laboratory measurements. A 90-nm CMOS comparator is measured to have an equivalent input-referred random noise of 0.73 mVrms for dc inputs, matching simulation results with a short channel excess noise factor ? = 2.
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Characterization of random decision errors in clocked Comparators
2008 IEEE Custom Integrated Circuits Conference, 2008Co-Authors: Brian S Leibowitz, C J MaddenAbstract:Clocked Comparators have found widespread use in noise sensitive applications such as wireline receivers, A/D converters, and memory bit-line detectors. However, their nonlinear, time-varying behavior and discrete output levels have discouraged the use of traditional small-signal noise simulation techniques such as NOISE in SPICE. This paper asserts that the periodic noise analysis available from RF circuit simulators can provide insight into the intrinsic sampling and decision operations of clocked Comparators and help develop a linear periodically time-varying (LPTV) noise model that accurately predicts the decision error probability. Two Comparators are simulated and compared to laboratory measurements. A 90 nm CMOS comparator is measured to have an equivalent input-referred random noise of 0.73 mVrms for DC inputs, matching simulation results with a short channel excess noise factor gamma = 2.
Samaneh Babayan-mashhadi - One of the best experts on this subject based on the ideXlab platform.
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Analysis and design of dynamic Comparators in ultra-low supply voltages
2014 22nd Iranian Conference on Electrical Engineering (ICEE), 2014Co-Authors: Samaneh Babayan-mashhadi, Moein Sarvaghad-moghaddamAbstract:The need for ultra-low power and area-efficient analog-to-digital converters (ADCs) is pushing towards the use of low-voltage (LV) dynamic clocked Comparators to maximize power efficiency and speed. In this paper, a delay analysis for a conventional body-driven LV dynamic comparator is presented. Then based on the analysis results, the circuit of a conventional body-driven comparator is modified for fast operation even in small supply voltages. Simulation results in 90nm CMOS technology reveal that comparator delay time is remarkably reduced. The maximum clock frequency of the proposed comparator can be increased to 333 MHz and 50 MHz at supply voltages of 0.5V and 0.35V, while consuming 2.3μW and 184nW, respectively. The standard deviation of the input-referred offset voltage is 5.1mV at 0.5V supply.
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Analysis and design of a low-voltage low-power double-tail comparator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014Co-Authors: Samaneh Babayan-mashhadi, Reza LotfiAbstract:The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative Comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic Comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Post-layout simulation results in a 0.18- μm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 2.5 and 1.1 GHz at supply voltages of 1.2 and 0.6 V, while consuming 1.4 mW and 153 μW, respectively. The standard deviation of the input-referred offset is 7.8 mV at 1.2 V supply.
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Analysis of power in dynamic Comparators
2013 21st Iranian Conference on Electrical Engineering (ICEE), 2013Co-Authors: Samaneh Babayan-mashhadi, Mojtaba Daliri, Reza LotfiAbstract:The need for ultra low-power, area efficient and high speed analog-to-digital converters (ADCs) is pushing towards the use of dynamic Comparators to maximize speed, power efficiency and re-configurability. In this paper an analysis on the power of the dynamic Comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator power consumption and also fully explore the tradeoffs in dynamic comparator design such as offset voltage, power and speed. To validate the analytical expressions, the power is first derived analytically and then will be compared to the result of simulating a conventional dynamic comparator in 0.18μm CMOS. A good agreement between these two verifies the effectiveness of the presented analysis.
