The Experts below are selected from a list of 67257 Experts worldwide ranked by ideXlab platform

Tor Aamodt - One of the best experts on this subject based on the ideXlab platform.

  • Abstract Floating-Point to Fixed-Point Compilation and Embedded Architectural Support
    2014
    Co-Authors: Tor Aamodt
    Abstract:

    Recently, software utilities for automating the translation of oating-point signal-processing ap-plications written in ANSI C into xed-point versions have been presented. This dissertation investigates a novel xed-point instruction-set operation, Fractional Multiplication with internal Left Shift (FMLS), and an associated translation algorithm, Intermediate-Result-Proling based Shift Absorption (IRP-SA), that combine to enhance xed-point rounding-noise and runtime per-formance when supported by a utility that directly targets the instruction set. A signicant feature of FMLS is that it is well suited to the latest generation of embedded processors that maintain relatively homogeneous register architectures. FMLS may improve the rounding-noise performance of fractional multiplication operations in several ways depending upon the specic xed-point scaling properties an application exhibits. The IRP-SA algorithm enhances this by exploiting the modular nature of 2's-Complement Addition, which allows the discarding of most-signi cant-bits that are redundant due to inter-operand correlations that often arise, for example, in recursive lters with poles close to the unit circle. Rounding-noise reductions equivalent to car-rying as much as 2.0 Additional bits of precision throughout the computation are demonstrated. Furthermore, by encoding a set of only four shift distances into the FMLS operation, speedup

  • Embedded ISA Support for Enhanced Floating-Point to Fixed-Point ANSI C Compilation
    2000
    Co-Authors: Tor Aamodt, Paul Chow
    Abstract:

    Recently tools for automating the translation of oatingpoint signal-processing applications written in ANSI C into fixed-point have been presented [32, 16, 8]. This paper introduces a novel fixed-point instruction-set operation, Fractional Multiplication with internal Left Shift (FMLS), and an associated translation algorithm--Intermediate-Result- Profiling based Shift Absorption (IRP-SA), that enhance fixedpoint rounding-noise and runtime performance. A significant feature of FMLS is that it is well suited to the latest generation of embedded processors that maintain relatively homogeneous register architectures. FMLS may improve the rounding-noise performance of fractional multiplication operations in three ways depending upon the speci c fixed-point scaling properties an application exhibits. The IRP-SA algorithm enhances this by exploiting the modular nature of 2's-Complement Addition which allows the discarding of most-significant-bits that are redundant due to inter-operand correlati..

  • Embedded ISA Support for Enhanced Floating-Point to Fixed-Point ANSI C Compilation
    2000
    Co-Authors: Tor Aamodt
    Abstract:

    Recently tools for automating the translation of floatingpoint signal-processing applications written in ANSI C into fixed-point have been presented [34, 17, 8]. This paper introduces a novel fixed-point instruction-set operation, Fractional Multiplication with internal Left Shift (FMLS), and an associated translation algorithm—Intermediate-Result-Profiling based Shift Absorption (IRP-SA), that enhance fixedpoint rounding-noise and runtime performance. A significant feature of FMLS is that it is well suited to the latest generation of embedded processors that maintain relatively homogeneous register architectures. FMLS may improve the rounding-noise performance of fractional multiplication operations in three ways depending upon the specific fixed-point scaling properties an application exhibits. The IRP-SA algorithm enhances this by exploiting the modular nature of 2’s-Complement Addition which allows the discarding of most-significant-bits that are redundant due to inter-operand correlations. Rounding-noise reductions equivalent to carrying as much as 2.0 Additional bits of precision throughout the computation are presented. Furthermore, by encoding a very limited set of output shift values (two left, one left, none, and one right) into the FMLS operation, speedups of up to 13 percent are observed. 1

Paul Chow - One of the best experts on this subject based on the ideXlab platform.

  • Embedded ISA Support for Enhanced Floating-Point to Fixed-Point ANSI C Compilation
    2000
    Co-Authors: Tor Aamodt, Paul Chow
    Abstract:

    Recently tools for automating the translation of oatingpoint signal-processing applications written in ANSI C into fixed-point have been presented [32, 16, 8]. This paper introduces a novel fixed-point instruction-set operation, Fractional Multiplication with internal Left Shift (FMLS), and an associated translation algorithm--Intermediate-Result- Profiling based Shift Absorption (IRP-SA), that enhance fixedpoint rounding-noise and runtime performance. A significant feature of FMLS is that it is well suited to the latest generation of embedded processors that maintain relatively homogeneous register architectures. FMLS may improve the rounding-noise performance of fractional multiplication operations in three ways depending upon the speci c fixed-point scaling properties an application exhibits. The IRP-SA algorithm enhances this by exploiting the modular nature of 2's-Complement Addition which allows the discarding of most-significant-bits that are redundant due to inter-operand correlati..

Adrian Willenbucher - One of the best experts on this subject based on the ideXlab platform.

  • a new algorithm for carry free Addition of binary signed digit numbers
    Field-Programmable Custom Computing Machines, 2014
    Co-Authors: Klaus Schneider, Adrian Willenbucher
    Abstract:

    Signed-digit (SD) numbers generalize traditional radix numbers by allowing negative digits within a certain range. Typically, this leads to redundant number representations that can be used to avoid the carry propagation problem of Addition of radix numbers. Unfortunately, as proved by Avizienis, the standard algorithm for carry-free Addition of SD numbers does not work for the binary case. In this paper, we therefore construct a special algorithm for the carry-free Addition and subtraction of binary SD numbers, i.e., Addition and subtraction of n-digit numbers are performed with circuits of depth O(1) and size O(n). This is possible by computing in Addition to the transfer digits used by the standard algorithm one Additional bit that allows us to distinguish relevant cases to avoid propagation of dependencies. The Additional bit and the transfer digit used to compute the sum digit at position i depend only on the summands' digits at positions i and i -- 1 so that all sum digits can be computed with a hardware circuit of a depth that is independent of the number of digits. We first explain the basics of the standard Addition algorithm to derive the Additional information needed to fix the algorithm for the binary case. After proving the correctness of our algorithm, we present experimental results that show that our implementation clearly outperforms two's Complement Addition even for small numbers, and saves 50% of the required chip area compared to other carry-free implementations.

Aamodt Tor - One of the best experts on this subject based on the ideXlab platform.

  • Floating-point to Fixed-point Compilation and Embedded Architectural Support
    2001
    Co-Authors: Aamodt Tor
    Abstract:

    grantor: University of TorontoRecently, software utilities for automating the translation of floating-point signal-processing applications written in ANSI~C into fixed-point versions have been presented. This dissertation investigates a novel fixed-point instruction-set operation, Fractional Multiplication with internal Left Shift (FMLS), and an associated translation algorithm, Intermediate-Result-Profiling based Shift Absorption (IRP-SA), that combine to enhance fixed-point rounding-noise and runtime performance when supported by a utility that directly targets the instruction set. A significant feature of FMLS is that it is well suited to the latest generation of embedded processors that maintain relatively homogeneous register architectures. The IRP-SA algorithm enhances this by exploiting the modular nature of 2's-Complement Addition, which allows the discarding of most-significant-bits that are redundant due to inter-operand correlations. Rounding-noise reductions equivalent to carrying as much as 2.0 Additional bits of precision throughout the computation and speedups of up to 13 percent are demonstrated.M.A.Sc

Xiao Li Zheng - One of the best experts on this subject based on the ideXlab platform.

  • simulation of the fixed point number arithmetic
    Key Engineering Materials, 2011
    Co-Authors: Feng Wang, Xiao Li Zheng
    Abstract:

    The fixed-point number arithmetic is always the key and difficult point of the computer organization. It is the basic knowledge of the computer organization. Because there are many operation methods of the fixed-point number and the operation process of it is complicated, the fixed-point number arithmetic is not easy for students to learn. The lack of the software to help the students do simulation computation is the biggest problem in the current teaching of the knowledge. To solve the problem, the simulation software of the fixed-point number arithmetic is developed with C++builder. The software is made up of "the fixed-point integer two's Complement Addition" module, "the fixed-point decimals two's Complement Addition" module, "the fixed-point integer two's Complement subtraction" module, "the fixed-point decimals two's Complement subtraction" module, "the sign-magnitude 1-bit multiplication"module, "the Booth's Algorithm"module, "the sign-magnitude two bits multiplication"module, "the two's Complement two bits multiplication"module, "the sign-magnitude recovery remainder division"module, "the sign-magnitude unrecovery remainder division"module, "the two's Complement unrecovery remainder division"module, etc. In order to test the simulation software, the test case is designed for the fixed-point arithmetic. According to the designed test case，the detailed test is carried out. The test results show that its simulation effect is good. The simulation software realizes the Addition, subtraction, multiplication, and division of the fixed-point number successfully. The CAI (computer-assisted instruction) can be carried out through the software. The software can help the students be familiar with and master the fixed-point number arithmetic rapidly.