The Experts below are selected from a list of 14790 Experts worldwide ranked by ideXlab platform
Chinteng Lin - One of the best experts on this subject based on the ideXlab platform.
-
vlsi architecture for the low Computation Cycle and power efficient recursive dft idft design
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2007Co-Authors: Landa Van, Chinteng LinAbstract:In this paper, we propose one low-Computation Cycle and power-efficient recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architecture adopting a hybrid of input strength reduction, the Chebyshev polynomial, and register-splitting schemes. Comparing with the existing recursive DFT/IDFT architectures, the proposed recursive architecture achieves a reduction in Computation-Cycle by half. Appling this novel low-Computation Cycle architecture, we could double the throughput rate and the channel density without increasing the operating frequency for the dual tone multi-frequency (DTMF) detector in the high channel density voice over packet (VoP) application. From the chip implementation results, the proposed architecture is capable of processing over 128 channels and each channel consumes 9.77 μW under 1.2 [email protected] in TSMC 0.13 1P8M CMOS process. The proposed VLSI implementation shows the power-efficient advantage by the low-Computation Cycle architecture.
-
low Computation Cycle and high speed recursive dft idft vlsi algorithm and architecture
Signal Processing Systems, 2005Co-Authors: Landa Van, Chunming Huang, Chinteng LinAbstract:In this paper, we propose two low-Computation Cycle and high-speed recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architectures adopting the hybrid of Chebyshev polynomial and register-splitting scheme. The proposed core-type recursive architecture achieves half Computation-Cycle reduction as well as less critical period compared with the conventional second-order DFT/IDFT architecture. So as to further reduce the number of Computation Cycles, based on the new core-type design, we develop the folded-type recursive DFT/IDFT architecture with the same operating frequency. Moreover, from the derivation results, the operation of DFT and IDFT can be performed with the same structure under different configurations.
Muhtian Shiue - One of the best experts on this subject based on the ideXlab platform.
-
a low Computation Cycle design of input decimation technique for ridft algorithm
European Signal Processing Conference, 2019Co-Authors: Chunhung Chen, Muhtian ShiueAbstract:In this paper, a low-Computation-Cycle and energy-efficient design of input-decimation technique for the recursive inverse discrete Fourier transform (RIDFT) algorithm is proposed for the high-speed broadband communication systems. It is crucial that the input-decimation technique is presented to decrease the number of input sequences for the recursive filter so that the Computation Cycle of RIDFT can be shortened to meet the computing time requirement (3.6 μs). Therefore, the input-decimation RIDFT algorithm is able to carry out at least 55.5% reduction of the total Computation Cycles compared with the considered algorithms. Holding the advantages of input-decimation technique, the Computational complexities of the real-multiplication and -addition are reduced to 41.3% and 22.2%, respectively. Finally, the physical implementation results show that the core area is 0.37× 0.37mm2 with 0.18 μm CMOS process. The power consumption is 5.16 mW with the supply voltage of 1.8 V and the operating clock of 40 MHz. The proposed design can achieve 258 million of Computational efficiency per unit area (CEUA) and really outperform the previous works.
Landa Van - One of the best experts on this subject based on the ideXlab platform.
-
vlsi architecture for the low Computation Cycle and power efficient recursive dft idft design
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2007Co-Authors: Landa Van, Chinteng LinAbstract:In this paper, we propose one low-Computation Cycle and power-efficient recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architecture adopting a hybrid of input strength reduction, the Chebyshev polynomial, and register-splitting schemes. Comparing with the existing recursive DFT/IDFT architectures, the proposed recursive architecture achieves a reduction in Computation-Cycle by half. Appling this novel low-Computation Cycle architecture, we could double the throughput rate and the channel density without increasing the operating frequency for the dual tone multi-frequency (DTMF) detector in the high channel density voice over packet (VoP) application. From the chip implementation results, the proposed architecture is capable of processing over 128 channels and each channel consumes 9.77 μW under 1.2 [email protected] in TSMC 0.13 1P8M CMOS process. The proposed VLSI implementation shows the power-efficient advantage by the low-Computation Cycle architecture.
-
low Computation Cycle and high speed recursive dft idft vlsi algorithm and architecture
Signal Processing Systems, 2005Co-Authors: Landa Van, Chunming Huang, Chinteng LinAbstract:In this paper, we propose two low-Computation Cycle and high-speed recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architectures adopting the hybrid of Chebyshev polynomial and register-splitting scheme. The proposed core-type recursive architecture achieves half Computation-Cycle reduction as well as less critical period compared with the conventional second-order DFT/IDFT architecture. So as to further reduce the number of Computation Cycles, based on the new core-type design, we develop the folded-type recursive DFT/IDFT architecture with the same operating frequency. Moreover, from the derivation results, the operation of DFT and IDFT can be performed with the same structure under different configurations.
Chunhung Chen - One of the best experts on this subject based on the ideXlab platform.
-
a low Computation Cycle design of input decimation technique for ridft algorithm
European Signal Processing Conference, 2019Co-Authors: Chunhung Chen, Muhtian ShiueAbstract:In this paper, a low-Computation-Cycle and energy-efficient design of input-decimation technique for the recursive inverse discrete Fourier transform (RIDFT) algorithm is proposed for the high-speed broadband communication systems. It is crucial that the input-decimation technique is presented to decrease the number of input sequences for the recursive filter so that the Computation Cycle of RIDFT can be shortened to meet the computing time requirement (3.6 μs). Therefore, the input-decimation RIDFT algorithm is able to carry out at least 55.5% reduction of the total Computation Cycles compared with the considered algorithms. Holding the advantages of input-decimation technique, the Computational complexities of the real-multiplication and -addition are reduced to 41.3% and 22.2%, respectively. Finally, the physical implementation results show that the core area is 0.37× 0.37mm2 with 0.18 μm CMOS process. The power consumption is 5.16 mW with the supply voltage of 1.8 V and the operating clock of 40 MHz. The proposed design can achieve 258 million of Computational efficiency per unit area (CEUA) and really outperform the previous works.
Sheaufang Lei - One of the best experts on this subject based on the ideXlab platform.
-
low Computation Cycle power efficient and reconfigurable design of recursive dft for portable digital radio mondiale receiver
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2010Co-Authors: Shinchi Lai, Wenho Juang, Chialin Chang, Chenchieh Lin, Chinghsing Luo, Sheaufang LeiAbstract:Low-cost, fast-Computational, power-efficient, and reconfigurable design for recursive discrete Fourier transform (RDFT) is proposed in this brief. The proposed method is the first integration that collated both the prime factor algorithm (PFA) and the Chinese reminder theorem (CRT) into a recursive algorithm. Hence, a multiCycle RDFT algorithm (PFA + CRT + RDFT) and its hardware implementation are produced and presented here in great detail. Compared with some well-known recursive algorithms, the significant improvements for the proposed algorithm can be summarized as follows: 1) The number of Computational Cycles of the proposed algorithm can be saved by up to 88.5%; 2) The number of multiplications and additions for the proposed algorithm is dramatically reduced by up to 85.2% and 85.2%, respectively; 3) The amount of coefficient read-only memory for storing the twiddle factors totally takes 694 words fewer than those of other existing RDFT algorithms; 4) The hardware cost of the proposed algorithm only takes four real multipliers and eight real adders. This design is more suitable for digital radio mondiale (DRM) systems, such as coded orthogonal frequency-division-multiplexing modulation. The proposed RDFT algorithm was designed and fabricated using a 0.18-μm 1P6M CMOS process. The core area is 521 × 508 μm2, and this hardware accelerator only consumes 8.44 mW at 25 MHz. Furthermore, the performance index of power for this design is three times discrete Fourier transform (DFT) per energy of previous work. Additionally, it can calculate the 288/256/176/112-point DFTs for a portable DRM receiver.