The Experts below are selected from a list of 579 Experts worldwide ranked by ideXlab platform
Madhava Syamlal - One of the best experts on this subject based on the ideXlab platform.
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DEVELOPMENT OF TECHNOLOGIES AND ANALYTICAL CAPABILITIES FOR VISION 21 ENERGY PLANTS
2002Co-Authors: Madhava SyamlalAbstract:A software design review meeting was conducted (Task 2.0). A CFD Viewer was developed, to allow the process analyst to view CFD results from the process simulator (Task 2.14). Work on developing a CO wrapper for the INDVU code was continued (Task 2.15). The model-edit GUI was modified to allow the user to specify a solution strategy. Enhancements were made to the solution strategy implementation (Task 2.16). Testing of the integrated software was continued and several bug fixes and enhancements were made: ability to expose CFD parameters to the process analyst and support for velocity and pressure inlet boundary conditions (Task 2.21). Work on preparing the release version progressed: Version 0.3 of V21 Controller was released, a global Configuration Dialog was implemented, and a code review process was initiated (Task 2.24). The calibration of the tube bank CFD model for the RPL AIChE Annual Meeting, November 8, 2002; and the Vision 21 Simulation meeting at Iowa State University, November 19-20, 2002 (Task 7.0).
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DEVELOPMENT OF TECHNOLOGIES AND ANALYTICAL CAPABILITIES FOR VISION 21 ENERGY PLANTS
Fluent Inc. (United States), 2002Co-Authors: Madhava SyamlalAbstract:A software design review meeting was conducted (Task 2.0). A CFD Viewer was developed, to allow the process analyst to view CFD results from the process simulator (Task 2.14). Work on developing a CO wrapper for the INDVU code was continued (Task 2.15). The model-edit GUI was modified to allow the user to specify a solution strategy. Enhancements were made to the solution strategy implementation (Task 2.16). Testing of the integrated software was continued and several bug fixes and enhancements were made: ability to expose CFD parameters to the process analyst and support for velocity and pressure inlet boundary conditions (Task 2.21). Work on preparing the release version progressed: Version 0.3 of V21 Controller was released, a global Configuration Dialog was implemented, and a code review process was initiated (Task 2.24). The calibration of the tube bank CFD model for the RP&L case was completed. While integrating the tube bank CFD model into the flow sheet model, several development requirements were identified and communicated to the developers. The requirements of porting V21 Controller and Configuration Wizard to FLUENT 6.1, turning off the transfer of temperature dependent properties, exposing CFD parameters in Aspen Plus and supporting velocity boundary conditions have been implemented (Task 4.1). An initial grid for the HRSG component has been prepared (Task 4.2). A web-based advisory board meeting was conducted on December 18, 2003 (Task 5.0). Project personnel attended and gave presentations at the Aspen World Conference, October 28-30, 2002; AIChE Annual Meeting, November 8, 2002; and the Vision 21 Simulation meeting at Iowa State University, November 19-20, 2002 (Task 7.0)
Christian Winter - One of the best experts on this subject based on the ideXlab platform.
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A Versatile Software Framework for Rapid Development of Signal and Image Processing Algorithms
2005Co-Authors: Stephan Rupp, Christian WinterAbstract:Digital signal and image processing are at the forefront of information technology and therefore frequently integrated into the syllabus of technical studies. The student's ambition is to come to terms with the content of the curriculum and gain experience how to apply theory when practicing on lab classes. In this contribution, we present a framework supporting students in focussing on the functional aspect of the solution when working on the lectures' excercises. Within the framework, processing steps are modelled as software components encapsulating a problem-specific algorithm. Secondary aspects of algorithm development - such as Configuration Dialog programming or memory management - are kept off the student and treated by the framework. Our approach is designed to be independent from any graphical user interface, however a virtual programming environment is provided, allowing the student to rapidly develop programs as being assembled as chains of the components. The user simply defines the dataflow as connections between the software components visually and performs the components' Configuration by means of automatically rendered settings Dialogs.
Stephan Rupp - One of the best experts on this subject based on the ideXlab platform.
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A Versatile Software Framework for Rapid Development of Signal and Image Processing Algorithms
2005Co-Authors: Stephan Rupp, Christian WinterAbstract:Digital signal and image processing are at the forefront of information technology and therefore frequently integrated into the syllabus of technical studies. The student's ambition is to come to terms with the content of the curriculum and gain experience how to apply theory when practicing on lab classes. In this contribution, we present a framework supporting students in focussing on the functional aspect of the solution when working on the lectures' excercises. Within the framework, processing steps are modelled as software components encapsulating a problem-specific algorithm. Secondary aspects of algorithm development - such as Configuration Dialog programming or memory management - are kept off the student and treated by the framework. Our approach is designed to be independent from any graphical user interface, however a virtual programming environment is provided, allowing the student to rapidly develop programs as being assembled as chains of the components. The user simply defines the dataflow as connections between the software components visually and performs the components' Configuration by means of automatically rendered settings Dialogs.
Namjin Kim - One of the best experts on this subject based on the ideXlab platform.
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FIR/IIR Filtering System Design
Digital Signal Processing System-Level Design Using LabVIEW, 2005Co-Authors: Nasser Kehtarnavaz, Namjin KimAbstract:This chapter focuses on finite impulse response (FIR) and an infinite impulse response (IIR) filter, which are designed using the virtual instruments (Vis) as a part of the digital filter design (DFD) toolkit. A lowpass FIR filter is generally designed by providing the appropriate specifications as per requirement by using a DFD toolkit. The specifications of the filter are mentioned in the Configuration Dialog box. Additional information on the designed filter, such as phase, group delay, impulse response, unit response, frequency response, and zero or pole plot can be known by using the DFD filter analysis express virtual instrument (VI). Creating a filtering system VI consists of signal generation, filtering, and graphical output components. Three sinusoidal signals are summed and passed through the designed FIR filter and the resulting filtered signal is then displayed and verified. In an IIR filter, specifications are provided as per requirement and the design of an IIR filter is achieved by using the DFD classical filter design express VI. Various tools are used to compute coefficient sets of digital filters based on their specifications; these are explained in the chapter.
Thomas A. Werne - One of the best experts on this subject based on the ideXlab platform.
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MicroShell Minimalist Shell for Xilinx Microprocessors
2011Co-Authors: Thomas A. WerneAbstract:MicroShell is a lightweight shell environment for engineers and software developers working with embedded microprocessors in Xilinx FPGAs. (MicroShell has also been successfully ported to run on ARM Cortex-M1 microprocessors in Actel ProASIC3 FPGAs, but without project-integration support.) Micro Shell decreases the time spent performing initial tests of field-programmable gate array (FPGA) designs, simplifies running customizable one-time-only experiments, and provides a familiar-feeling command-line interface. The program comes with a collection of useful functions and enables the designer to add an unlimited number of custom commands, which are callable from the command-line. The commands are parameterizable (using the C-based command-line parameter idiom), so the designer can use one function to exercise hardware with different values. Also, since many hardware peripherals instantiated in FPGAs have reasonably simple register-mapped I/O interfaces, the engineer can edit and view hardware parameter settings at any time without stopping the processor. MicroShell comes with a set of support scripts that interface seamlessly with Xilinx's EDK tool. Adding an instance of MicroShell to a project is as simple as marking a check box in a library Configuration Dialog box and specifying a software project directory. The support scripts then examine the hardware design, build design-specific functions, conditionally include processor-specific functions, and complete the compilation process. For code-size constrained designs, most of the stock functionality can be excluded from the compiled library. When all of the configurable options are removed from the binary, MicroShell has an unoptimized memory footprint of about 4.8 kB and a size-optimized footprint of about 2.3 kB. Since MicroShell allows unfettered access to all processor-accessible memory locations, it is possible to perform live patching on a running system. This can be useful, for instance, if a bug is discovered in a routine but the system cannot be rebooted: Shell allows a skilled operator to directly edit the binary executable in memory. With some forethought, MicroShell code can be located in a different memory location from custom code, permitting the custom functionality to be overwritten at any time without stopping the controlling shell.