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Carlos Julio Tierracriollo - One of the best experts on this subject based on the ideXlab platform.
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a low cost portable micro controlled device for multi channel led visual stimulation
Journal of Neuroscience Methods, 2011Co-Authors: Marcos Antonio Da Silva Pinto, John Kennedy Schettino De Souza, Jerome Baron, Carlos Julio TierracriolloAbstract:Abstract Light emitting diodes (LEDs) are extensively used as light sources to investigate visual and visually related function and dysfunction. Here, we describe the design of a compact, low-cost, stand-alone LED-based system that enables the Configuration, storage and presentation of elaborate visual stimulation paradigms. The core functionality of this system is provided by a microcontroller whose ultra-low power consumption makes it well suited for long lasting battery applications. The effective use of hardware resources is managed by multi-layered architecture software that provides an intuitive and user-friendly interface. In the Configuration Mode, different stimulation sequences can be created and memorized for ten channels, independently. LED-driving current output can be set either as continuous or pulse modulated, up to 500 Hz, by duty cycle adjustments. In run Mode, multiple-channel stimulus sequences are automatically applied according to the pre-programmed protocol. Steady state visual evoked potentials were successfully recorded in five subjects with no visible electromagnetic interferences from the stimulator, demonstrating the efficacy of combining our prototyped equipment with electrophysiological techniques. Finally, we discuss a number of possible improvements for future development of our project.
Mao Minghe - One of the best experts on this subject based on the ideXlab platform.
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iec international electrotechnical commission 61850 based visual graphics Configuration method and iec61850 based visual graphics Configuration system
2014Co-Authors: Cao Ning, Liu Tian-shi, Ding Yan, Mao MingheAbstract:The invention discloses an IEC (international electrotechnical commission) 61850-based visual graphics Configuration method and an IEC61850-based visual graphics Configuration system. The IEC61850-based visual graphics Configuration system comprises a basic drawing module, an electric graphics primitive module, an attribute editing module, a secondary function module, a combination operation module and a file generation module. Visual graphics replace complicated text information, levels of the Configuration information are represented by topological structures of the graphics, and users and the graphics interact with one another, so that SCL (substation Configuration language) Configuration files which meet requirements can be generated. The IEC61850-based visual graphics Configuration method and the IEC61850-based visual graphics Configuration system have the advantages that the traditional text Configuration Mode is converted into a visual graphics Configuration Mode, and accordingly Configuration work can be simplified; the Configuration information is associated with the visual graphics, so that SVG (scalable vector graphics) with the Configuration information can be automatically generated.
Marcos Antonio Da Silva Pinto - One of the best experts on this subject based on the ideXlab platform.
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a low cost portable micro controlled device for multi channel led visual stimulation
Journal of Neuroscience Methods, 2011Co-Authors: Marcos Antonio Da Silva Pinto, John Kennedy Schettino De Souza, Jerome Baron, Carlos Julio TierracriolloAbstract:Abstract Light emitting diodes (LEDs) are extensively used as light sources to investigate visual and visually related function and dysfunction. Here, we describe the design of a compact, low-cost, stand-alone LED-based system that enables the Configuration, storage and presentation of elaborate visual stimulation paradigms. The core functionality of this system is provided by a microcontroller whose ultra-low power consumption makes it well suited for long lasting battery applications. The effective use of hardware resources is managed by multi-layered architecture software that provides an intuitive and user-friendly interface. In the Configuration Mode, different stimulation sequences can be created and memorized for ten channels, independently. LED-driving current output can be set either as continuous or pulse modulated, up to 500 Hz, by duty cycle adjustments. In run Mode, multiple-channel stimulus sequences are automatically applied according to the pre-programmed protocol. Steady state visual evoked potentials were successfully recorded in five subjects with no visible electromagnetic interferences from the stimulator, demonstrating the efficacy of combining our prototyped equipment with electrophysiological techniques. Finally, we discuss a number of possible improvements for future development of our project.
Edmundo Roberto Mauro - One of the best experts on this subject based on the ideXlab platform.
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Implementação do protocolo X-25 num concentrador de comunicações baseado no 8088
[s.n.], 2018Co-Authors: Edmundo Roberto MauroAbstract:Orientador: Celio Cardoso GuimarãesDissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Matematica, Estatistica e Ciencia da ComputaçãoResumo: Não informado.Abstract: This work presents an implementation of the X-25 communication protocol, which is defined for the: CCITT Recommendation (Committee Consultative International Telegraph and Telephone),on an Intel 8088 microprocessador [201, [231 and [36]. The proposed system is based on message exchange. The microprocessor has the function of a concentrator linked to a packet switching network. It will communicate on one side with a network node and on other side with several terminals. The Configuration Mode between the concentrator and the network node is balanced asynchronous. As an objective, the levels 1 and 2 change through hardware and software a not very reliable point-to-point link into a reliable link. As an second objective, participants in the network exchange traffic information to avoid congestion. The level 3 executes multiplexing to change a single level 2 logical circuit into several independent logical channels. At the level 4 (transport level) some end-to-end control functions are implemented. The levels 2, 3 and 4, in addition to a Manager (Supervisor) and the X-25 line reception and transmission interrupt routines are all treated as concurrent processes. In this work, we also use a formal technique analyse to protocols in such a way as to prevent them against deadlock, unspecified receptions, nonexecutable interactions and state ambiguities as proposed by P. Zafiropulo [19]. We made an analysis of the several levels specifications. An HDLC 8273 interface is used to implement physical the link between the microprocessor and the network. The prototype developed for this thesis possesses two HDLC 8273 interfaces and 32K RAM memory. The programs executed on the 8088 are remotely loaded from the DEC-10 system of the Computing Center. In Chapter I, we describe the ISO architecture and the X-25 protocol. We specify the level 4 used for the purpose of this the sis. State diagram were produced for level 2, from the X-25 protocol specification text for level 3, extracted from the X-25 specification, and for level 4, from the specification of this thesis. In Chapter 11, we formally analyse the X-25 protocol guarantee that it is an error-free protocol. The analysis considers the state diagrams defined in Chapter 1. In Chapter III, we present a brief discussion about concurrent processing languages. where appropriate, comments on Módula 2, the chosen language for the implementation, were included. Communication and synchronization between concurrent processes using monitors and message exchange are presented. Examples. of the X-25 protocol implementation using this two Models are shown [3], [81] and [16]. In Chapter IV, which is the thesis body, we treat the implementation on the 8088 microprocessor. The system is .described as a whole and analysed with respect to the following important details: data structures, process communication, non-interrupt modules, dynamic memory allocation, timers, HDLC 8273 interface, etc. In Chapter V, we describe the debugging tests made on the system in a stepwise manner and the conclusion of thesis along with several suggestions were presented in Chapter VI. The main contributions of this thesis were: - Use of formal protocol analysis in a practical implementation of the X-25 protocol. An implementation methodology using message exchange between processes representing the protocol levels and explicit process control transference using the tools implemented in Modula 2.MestradoMestre em Ciência da Computaçã
Scott C Smith - One of the best experts on this subject based on the ideXlab platform.
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design and implementation of fpga Configuration logic block using asynchronous static ncl
IEEE Region 10 Conference, 2008Co-Authors: I P Dugganapally, Waleed K Alassadi, T Tammina, Scott C SmithAbstract:This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous static NULL convention logic (NCL) Library. The proposed design uses three static LUT's for implementing NCL logic functions. Each LUT can be configured to function as any one of the 27 fundamental NCL Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable and inverting variations. The CLB has two Modes: Configuration Mode and operation Mode. The static NCL FPGA CLB is simulated at the transistor level using the 1.8 V, 180 nm TSMC CMOS process.
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design and implementation of fpga Configuration logic block using asynchronous semi static ncl circuits
IEEE Region 10 Conference, 2008Co-Authors: I P Dugganapally, Waleed K Alassadi, V Pillai, Scott C SmithAbstract:This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous semi-static NULL convention logic (NCL) Library. The proposed design uses three semi-static LLT's for implementing NCL logic functions. Each LLT can be configured to function as any one of the 27 fundamental NCL Semi-Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable and inverting variations. The CLB has two Modes: Configuration Mode and Operation Mode. The Static NCL FPGA CLB is simulated at the transistor level using the 1.8 V, 180 nm TSMC CMOS process.