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Ali Sheikholeslami - One of the best experts on this subject based on the ideXlab platform.

  • content-addressable memory (CAM) circuits and architectures: A tutorial and survey
    IEEE Journal of Solid-State Circuits, 2006
    Co-Authors: Kostas Pagiamtzis, Ali Sheikholeslami
    Abstract:

    We survey recent developments in the design of large-capacity content-addressable memory (CAM). A CAM is a memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry. CAMs are especially popular in network routers for packet forwarding and packet classification, but they are also beneficial in a variety of other applications that require high-speed table lookup. The main CAM-design challenge is to reduce power consumption associated with the large amount of parallel active circuitry, without sacrificing speed or memory density. In this paper, we review CAM-design techniques at the circuit level and at the architectural level. At the circuit level, we review low-power matchline sensing techniques and searchline driving approaches. At the architectural level we review three methods for reducing power consumption.}, keywords={NAND circuits;NOR circuits;content-addressable storage;logic design;low-power electronics;NAND cell;NOR cell;bank selection;content addressable memory circuits;high-speed table lookup;lookup-table function;low-power matchline sensing techniques;matchline pipelining;network routers;packet classification;packet forwarding;parallel active circuitry;searchline driving;Application software;CADCAM;Circuits;Clocks;Computer aided manufacturing;Energy consumption;IP networks;Image coding;Table lookup;Tutorial;Bank selection;NAND cell;NOR cell;content-addressable memory (CAM);matchline pipelining;matchline sensing;review;searchline power

  • ISMVL - A multiple-valued ferroelectric content-addressable memory
    Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96), 1996
    Co-Authors: Ali Sheikholeslami, P.g. Gulak, T. Hanyu
    Abstract:

    A novel architecture for a multiple-valued ferroelectric content-addressable memory (FCAM) is proposed. An FCAM employs ferroelectric capacitors as storage elements to provide a nonvolatile content-addressable memory. A 2-bit search operation is performed by a simultaneous access to a 4-level polarization, hence reducing the total number of search operations to half. Four FCAM structures are discussed in terms of their speed, area, and implementation feasibility.

Noor Mahammad Sk - One of the best experts on this subject based on the ideXlab platform.

  • A Novel Ternary content-addressable memory (TCAM) Design Using Reversible Logic
    2015 28th International Conference on VLSI Design, 2015
    Co-Authors: Dinesh S Kumar, Noor Mahammad Sk
    Abstract:

    Content addressable memory is a special type of memory which can do search operation in a single clock cycle. CAM has disadvantages of high power dissipation during the matching operation. Ternary content addressable memory (TCAM) is a special type of memory which is used to search for logic 0, logic 1, logic 'x'. These types of memory are used in routers in order to perform the lookup table function in a single clock cycle. As the use of networks, typified by the Internet, has spread widely in recent years, attention has focused on TCAMs as a key device for increasing the speed of packet forwarding (packet data transfers) by networking equipment by enabling high-speed lookup of destinations, etc., for large volumes of information during packet data transfers. Reversible logic has gained its interest in recent years due to its ultra low power characteristics. Many works have been done to reduce the power consumption in TCAM. This paper deals with a novel design of TCAM cells using reversible logic. The proposed design is optimized in terms of number of garbage outputs and quantum cost. The proposed TCAM cell does the function of the conventional TCAM cell.

  • A novel binary content addressable memory design using reversible logic
    International Conference on Computing and Communication Technologies, 2014
    Co-Authors: Dinesh S Kumar, Noor Mahammad Sk
    Abstract:

    Content addressable memory is a special type of memory which can do search operation in a single clock cycle. CAM has disadvantages of high power dissipation during the matching operation. Binary content addressable memory (Bi-CAM) is a special type of memory which is used to search for logic 0, logic 1. These types of memories are used in computer networking devices in order to perform the look up table function in a single clock cycle. Reversible logic has gained its interest in recent years due to its minimum heat dissipation characteristics. Many works have been done to reduce the power consumption in BiCAM. This paper deals with a novel design of BiCAM cells using reversible logic. The design is optimized by reducing the number of garbage outputs and quantum cost. The proposed BiCAM cell does the function of the conventional BiCAM cell.

Dinesh S Kumar - One of the best experts on this subject based on the ideXlab platform.

  • A Novel Ternary content-addressable memory (TCAM) Design Using Reversible Logic
    2015 28th International Conference on VLSI Design, 2015
    Co-Authors: Dinesh S Kumar, Noor Mahammad Sk
    Abstract:

    Content addressable memory is a special type of memory which can do search operation in a single clock cycle. CAM has disadvantages of high power dissipation during the matching operation. Ternary content addressable memory (TCAM) is a special type of memory which is used to search for logic 0, logic 1, logic 'x'. These types of memory are used in routers in order to perform the lookup table function in a single clock cycle. As the use of networks, typified by the Internet, has spread widely in recent years, attention has focused on TCAMs as a key device for increasing the speed of packet forwarding (packet data transfers) by networking equipment by enabling high-speed lookup of destinations, etc., for large volumes of information during packet data transfers. Reversible logic has gained its interest in recent years due to its ultra low power characteristics. Many works have been done to reduce the power consumption in TCAM. This paper deals with a novel design of TCAM cells using reversible logic. The proposed design is optimized in terms of number of garbage outputs and quantum cost. The proposed TCAM cell does the function of the conventional TCAM cell.

  • A novel binary content addressable memory design using reversible logic
    International Conference on Computing and Communication Technologies, 2014
    Co-Authors: Dinesh S Kumar, Noor Mahammad Sk
    Abstract:

    Content addressable memory is a special type of memory which can do search operation in a single clock cycle. CAM has disadvantages of high power dissipation during the matching operation. Binary content addressable memory (Bi-CAM) is a special type of memory which is used to search for logic 0, logic 1. These types of memories are used in computer networking devices in order to perform the look up table function in a single clock cycle. Reversible logic has gained its interest in recent years due to its minimum heat dissipation characteristics. Many works have been done to reduce the power consumption in BiCAM. This paper deals with a novel design of BiCAM cells using reversible logic. The design is optimized by reducing the number of garbage outputs and quantum cost. The proposed BiCAM cell does the function of the conventional BiCAM cell.

S. Yajima - One of the best experts on this subject based on the ideXlab platform.

  • EURO-DAC - Linear time fault simulation algorithm using a content addressable memory
    Proceedings EURO-DAC '92: European Design Automation Conference, 1992
    Co-Authors: Nagisa Ishiura, S. Yajima
    Abstract:

    The authors present a new fast fault simulation algorithm using a content addressable memory, which deals with zero-delay fault simulation of gate-level synchronous sequential circuits. The new algorithm attempts to reduce the computation time by processing many faults at a time on the assumption that a content addressable memory can be regarded as a single instruction multiple data (SIMD) type parallel computation machine. According to theoretical estimation, the speed performance of a simulator based on the proposed algorithm is comparable to that of a fast fault simulator implemented on a vector supercomputer for a circuit of about 2400 gates. >

  • Linear time fault simulation algorithm using a content addressable memory
    Proceedings EURO-DAC '92: European Design Automation Conference, 1992
    Co-Authors: Nagisa Ishiura, S. Yajima
    Abstract:

    The authors present a new fast fault simulation algorithm using a content addressable memory, which deals with zero-delay fault simulation of gate-level synchronous sequential circuits. The new algorithm attempts to reduce the computation time by processing many faults at a time on the assumption that a content addressable memory can be regarded as a single instruction multiple data (SIMD) type parallel computation machine. According to theoretical estimation, the speed performance of a simulator based on the proposed algorithm is comparable to that of a fast fault simulator implemented on a vector supercomputer for a circuit of about 2400 gates.

J. Lamoureux - One of the best experts on this subject based on the ideXlab platform.