The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Takao Onoye - One of the best experts on this subject based on the ideXlab platform.
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trade off analysis between timing error rate and Power Dissipation for adaptive speed control with timing error prediction
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2009Co-Authors: Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao OnoyeAbstract:Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is promising to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and Power Dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using adders in subthreshold operation in a 90nm CMOS process. We show a trade-off between timing error rate and Power Dissipation, and reveal the dependency of the trade-off on design parameters.
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trade off analysis between timing error rate and Power Dissipation for adaptive speed control with timing error prediction
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao OnoyeAbstract:Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is a promising approach to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and Power Dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using a 32-bit ripple carry adder in subthreshold operation in a 90nm CMOS process. We show a trade-off between timing error rate and Power Dissipation, and reveal the dependency of the trade-off on design parameters.
Hiroshi Fuketa - One of the best experts on this subject based on the ideXlab platform.
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trade off analysis between timing error rate and Power Dissipation for adaptive speed control with timing error prediction
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2009Co-Authors: Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao OnoyeAbstract:Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is promising to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and Power Dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using adders in subthreshold operation in a 90nm CMOS process. We show a trade-off between timing error rate and Power Dissipation, and reveal the dependency of the trade-off on design parameters.
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trade off analysis between timing error rate and Power Dissipation for adaptive speed control with timing error prediction
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao OnoyeAbstract:Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is a promising approach to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and Power Dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using a 32-bit ripple carry adder in subthreshold operation in a 90nm CMOS process. We show a trade-off between timing error rate and Power Dissipation, and reveal the dependency of the trade-off on design parameters.
Yukio Mitsuyama - One of the best experts on this subject based on the ideXlab platform.
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trade off analysis between timing error rate and Power Dissipation for adaptive speed control with timing error prediction
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2009Co-Authors: Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao OnoyeAbstract:Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is promising to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and Power Dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using adders in subthreshold operation in a 90nm CMOS process. We show a trade-off between timing error rate and Power Dissipation, and reveal the dependency of the trade-off on design parameters.
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trade off analysis between timing error rate and Power Dissipation for adaptive speed control with timing error prediction
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao OnoyeAbstract:Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is a promising approach to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and Power Dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using a 32-bit ripple carry adder in subthreshold operation in a 90nm CMOS process. We show a trade-off between timing error rate and Power Dissipation, and reveal the dependency of the trade-off on design parameters.
Masanori Hashimoto - One of the best experts on this subject based on the ideXlab platform.
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trade off analysis between timing error rate and Power Dissipation for adaptive speed control with timing error prediction
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2009Co-Authors: Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao OnoyeAbstract:Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is promising to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and Power Dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using adders in subthreshold operation in a 90nm CMOS process. We show a trade-off between timing error rate and Power Dissipation, and reveal the dependency of the trade-off on design parameters.
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trade off analysis between timing error rate and Power Dissipation for adaptive speed control with timing error prediction
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao OnoyeAbstract:Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is a promising approach to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and Power Dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using a 32-bit ripple carry adder in subthreshold operation in a 90nm CMOS process. We show a trade-off between timing error rate and Power Dissipation, and reveal the dependency of the trade-off on design parameters.
Y Tsividis - One of the best experts on this subject based on the ideXlab platform.
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signal to noise ratio dynamic range and Power Dissipation paying attention to their interrelation can greatly benefit analog circuit design
IEEE Solid-State Circuits Magazine, 2018Co-Authors: Y TsividisAbstract:Low Power Dissipation is paramount in an increasing number of applications. These notably include the Internet of Things and wireless sensor networks, in which a battery must last a very long time (even ten years in some cases) or in which energy harvesting is used. Battery life is also a key consideration in more traditional applications such as hearing aids and communication devices. All of these applications involve analog signals and require careful microPower circuit design. Such design can be more efficient if guided by an understanding of the fundamental limits [1]-[4], beyond which nature does not allow us to go. In this article, we review the relation between Power Dissipation and signal-to-noise ratio (SNR) for analog circuits. We make a crucial distinction between SNR and usable dynamic range (UDR) and review ways to allow the SNR to vary as needed, thus extending the UDR and resulting in adaptive Power Dissipation.
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event driven ghz range continuous time digital signal processor with activity dependent Power Dissipation
IEEE Journal of Solid-state Circuits, 2012Co-Authors: Mariya Kurchuk, C Weltinwu, Dominique Morche, Y TsividisAbstract:Presented is a clockless, continuous-time (CT) GHz processor that bypasses some of the limitations of conventional digital and analog implementations. Per-edge digital signal encoding is used for parallel processing of continuous-time samples with a temporal spacing as narrow as 15 ps, generated by a 3-b CT flash ADC. Parallel digital delay chains and programmable charge pumps realize the asynchronous filtering operation, each consuming negligible Power while awaiting a new sample. A six-tap CT ADC and CT digital FIR processor system occupies 0.07 mm2 and achieves dynamic range of over 20 dB in the 0.8-3.2-GHz signal range. The system's rate of operations automatically adapts to the signal, thus causing its Power Dissipation to vary in the range of 1.1 to 10 mW according to input activity.
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ghz range continuous time programmable digital fir with Power Dissipation that automatically adapts to signal activity
International Solid-State Circuits Conference, 2011Co-Authors: Mariya Kurchuk, C Weltinwu, Dominique Morche, Y TsividisAbstract:GHz-range applications that operate in a variety of signal situations and/or multiple standards require highly programmable responses that cannot be provided by analog circuits. Conventional digital solutions suffer from aliasing, thus requiring a complicated antialiasing filter and/or extremely high clock speeds with high Power Dissipation. An alternative is continuous-time (CT) DSP [1], which uses level-crossing sampling [2] but without a clock. It offers activity-dependent Power Dissipation, is alias-free and has lower EMI emissions. This technique has so far been demonstrated in the voice band [3] but cannot be pushed beyond the MHz range because it involves extremely narrow pulse widths that cannot be handled by digital logic. This work bypasses this timing problem, enabling a five-orders-of-magnitude improvement in frequency capability compared to [3], thus making CT DSP a candidate for wideband GHz low-dynamic-range applications, such as those found in pulse radio, spectrum sensing, and channel equalization. Presented is a 3b 6-tap CT DSP system with wide programmability that is implemented in ST 65nm technology.
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dynamic range optimization of weakly nonlinear fully balanced gm c filters with Power Dissipation constraints
IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing, 2003Co-Authors: Y Palaskas, Y TsividisAbstract:This paper presents an analytical algorithm for optimizing the dynamic range of continuous-time active filters under a fixed Power Dissipation constraint. Assuming weak third-order nonlinearities, we model distortion as a small signal disturbance of the linear solution and use linear techniques in the distortion analysis. Due to the generality of the formulation many important distortion phenomena can be described, e.g., the compression of the desired in-band signal due to large out-of-band interferers, intermodulation distortion, etc. Simple, closed-form expressions are derived for the noise and the distortion of the filter as functions of Power Dissipation. These expressions are used to optimize the noise, distortion and dynamic range, of the filter. The validity of the proposed algorithm is verified with simulation.
